Flip flop design

Discussion in 'The Projects Forum' started by haykp, Feb 14, 2011.

  1. haykp

    Thread Starter New Member

    Oct 7, 2010
    18
    0
    Dear Forum,

    The attached picture is a schematic diagram of a Dff.

    As can be seen in that diagram the first input TG clock is CL and not CLK.

    What is the reason of this? Why we cannot conect the CLK to the clock of first TG.

    Thanks,
    Hayk Petrosyan
     
    • Dff.jpg
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  2. Wendy

    Moderator

    Mar 24, 2008
    20,765
    2,535
    The inverters I recognize, but not the boxes with slashes on them. What are they?
     
  3. Bernard

    AAC Fanatic!

    Aug 7, 2008
    4,170
    395
    CL is just buffered CLK. I guess the TGs, tranmission gate, are something like a 4066 with push-pull control?? Salesmen usted to try to be cool and talk about DIFF amps- just plain old 747 OP amps.
     
  4. Papabravo

    Expert

    Feb 24, 2006
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