Flip flop design

Thread Starter

haykp

Joined Oct 7, 2010
18
Dear Forum,

The attached picture is a schematic diagram of a Dff.

As can be seen in that diagram the first input TG clock is CL and not CLK.

What is the reason of this? Why we cannot conect the CLK to the clock of first TG.

Thanks,
Hayk Petrosyan
 

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Bernard

Joined Aug 7, 2008
5,784
CL is just buffered CLK. I guess the TGs, tranmission gate, are something like a 4066 with push-pull control?? Salesmen usted to try to be cool and talk about DIFF amps- just plain old 747 OP amps.
 
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