I need to create a finite state machine in Verilog. It's kind of like a mod-10 counter, but with some variations.
When,
w1w0 = 00 the count remains the same
w1w0 = 01 the count increases by one
w1w0 = 10 the count increases by two
w1w0 = 11 the count decreases by one
And then obviously, I want to display the counter on a 7-seg display.
Before I start to do the Verilog stuff, I want to make a state diagram that describes this machine. My textbook doesn't help me very much and I don't understand how to create transition, state, and state/output tables for the machine.
Can anyone give me some suggestions on where to start or some good resources to learn more about it? I'm working on it now and will post what I have later this evening, but I'm struggling here. Thank you in advance.
When,
w1w0 = 00 the count remains the same
w1w0 = 01 the count increases by one
w1w0 = 10 the count increases by two
w1w0 = 11 the count decreases by one
And then obviously, I want to display the counter on a 7-seg display.
Before I start to do the Verilog stuff, I want to make a state diagram that describes this machine. My textbook doesn't help me very much and I don't understand how to create transition, state, and state/output tables for the machine.
Can anyone give me some suggestions on where to start or some good resources to learn more about it? I'm working on it now and will post what I have later this evening, but I'm struggling here. Thank you in advance.