Finishing touches

Discussion in 'General Electronics Chat' started by deefactorial, Oct 10, 2008.

  1. deefactorial

    Thread Starter Active Member

    Jun 11, 2008
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    I've developed a circuit and I'm in the final stages of design. I have ordered all the parts, made the adjustments to the footprints, redesigned the via holes to match the "free drill sizes" for the vendor drill mapping. I feel I am ready to send the board to get printed.

    I was curious if anyone could take a look at the board and tell me if you see anything that would cause any concern. This is my first board and I'm hoping to get it right the first time.

    Some of the specific things that might be good to look at and advise me about are:

    1.the changing of trace line thickness close to the 100 pin TQFP microchip in the center. The minimum trace line thickness and spacing is .007 mil.

    2. the Trace lines from capacitors in the top right, I have a trace going to all the caps and then connect it to the ground plane at one place, I was wondering if it would have been better to connect the caps directly to the ground plane.

    3. Some of the ground plane sections are connected through very small entrances and I have added Vias tying both the top and bottom ground planes.

    Any advice is greatly appreciated. I'm grateful for all the advice I have received so far; I probably would not have gotten this far without it

    Thanks,
    Dominique
     
  2. scubasteve_911

    Senior Member

    Dec 27, 2007
    1,202
    1
    Hey,

    It looks pretty good. Without a schematic, I cannot really judge how well the layout is.

    1) You shouldn't route signals under your crystal, it's a high impedance circuit. The XTAL should be closer too, it's actually going through a lot to get to the micro.
    2) I would recommend having a VCC plane on top/bottom, and a GND plane on the other side. You seem to have two ground planes, then connecting them from top to bottom on occasion. Or, at least, run VCC to the capacitor, then the VCC node of the capacitor to the pin. Otherwise, you defeat the purpose of the capacitor. Your capacitors seem too far away, it really depends on how fast the microcontroller is operating and the speed of the IO.
    3) When connecting to through hole devices, thicken the trace a bit. Sometimes thin traces get poked out by a sloppy placement. It also makes the connection more robust from delaminating due to heat.
    4) If board is to be handled a lot, then consider an ESD ring around the PCB.

    Steve

    P.S.- Your company is okay with you posting this stuff? I would get hung if I did this :(
     
    Last edited: Oct 10, 2008
  3. hgmjr

    Moderator

    Jan 28, 2005
    9,030
    214
    The number of members that can provide you with assistance is going to be limited. That is because very few members have access to gerber viewers.

    Does you gerber software feature the ability to save the gerber files in png, pdf, or some other more generally available file format?

    hgmjr
     
  4. jpanhalt

    AAC Fanatic!

    Jan 18, 2008
    5,694
    904
    The last file in the unzipped folder is a PNG. John
     
  5. scubasteve_911

    Senior Member

    Dec 27, 2007
    1,202
    1
    Oh, and one more thing, which I eluded to earlier. Your bulk caps after your two linear regulators should be the connection to VCC, not from the linear regulators themselves. This is defeating the purpose, as with the micro's bypass caps mentioned earlier.

    By the way, nice job for your first PCB! My first PCB had about 800$ in parts on it, along with many long hours of work, and it didn't work :( I learned a lot from it though, in form of a 'nazi-like' checkover of the full-design when I am finished :)

    Steve
     
  6. deefactorial

    Thread Starter Active Member

    Jun 11, 2008
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    0
    The crystal can be 8Mhz or 20Mhz. And the IO will probably not go any faster than a serial interface.
    I will re-route the crystals.

    I will beef up the traces before they enter any through hole components.

    I guess I will have to switch the top plane from a ground plane to a VCC plane. This is going to take a lot of work. But I do see what you mean about how the capacitors will be useless.

    How can I get the capacitors any closer to the chip? the traces have to go around the cap and into the chip while still maintaining a .007mil space in between everything.

    what is a ESD ring ? does ESD stand for electrostatic discharge ? What does one look like and how is it wired?

    I'm not too worried about stolen intellectual property, no one knows the application of this circuit and they don't have the original files to make modifications. It would be really hard for someone other than myself to make use of this circuit, and I guess I'm not finished.
     
  7. scubasteve_911

    Senior Member

    Dec 27, 2007
    1,202
    1
    Hey,

    The plane does not need to be a VCC plane, it was just a suggestion. Generally, it works out fairly well from a routing point of view and the fact that this generates a free capacitance distributed across the PCB (VCC - Dielectric - GND).

    Part of PCB design is knowing what is critical and what is not. Things like the crystal and sensitive circuitry should be isolated from the rest and routed closely to prevent higher risk of influence by other traces. I usually place the capacitor directly in front of the pin I am decoupling, then route everything around the capacitor. This is why placement is key before doing any routing, but understanding where things need to be is all a function of experience.

    The beefing up of the traces around connectors is more important than things like DIPs. Their leads are much heavier and are more prone to causing damage, along with the fact that they require a bit more heat when soldering. I should have specified that.

    You don't need to change the capacitor layout, just where the VCC is taken from. You currently are taking it from the regulator, where it should ideally be taken from the bulk capacitors.

    The ESD ring is a star-grounded ring that goes around the PCB to protect it from shocks during handling. This is only for when you expect the PCB to have a high risk of ESD, so typically for development PCBs, etc. If it is being installed, I wouldn't worry about it.

    Your board should work as expected the way it is, I am just making note of some changes that would increase the performance. It may not be a significant gain, but are just good design practices. Sometimes, depending on the design, it is not possible to implement good design practices.

    Good luck!

    Steve

    P.S. - Yeah, I guess without the code and intended application, it would be pretty useless IP. Nonetheless, business people in the company may not understand that and freak out about it.
     
  8. deefactorial

    Thread Starter Active Member

    Jun 11, 2008
    33
    0
    I have finished changing the top ground plane into a 3.3v positive power plane. I've attached an image.

    I changed all the traces going into through hole devices to a power trace rather than a signal trace. so the connection between the pins and the traces is more solid.

    I moved the crystals so they are closer and nothing crosses their paths.

    I tried to move the caps closer to the devices.

    I was wondering if vias under the devices makes a difference in the clearance under the devices?

    I have not had a chance to make a ESD ring, and I still don't know what I would ground it to, The mounting holes, or the ground plane ? And does the ESD ring have solder mask on it ? I hope I will be fine without one, because I would have to move a lot of components around to make space for it and it will be mounted onto another device.

    Thank you for all the help, It has been indispensable.
     
  9. scubasteve_911

    Senior Member

    Dec 27, 2007
    1,202
    1
    Looks good.

    The vias under devices can be a tricky thing. Vias tend to suck solder away from the joint if there is a void in soldermask, thus weakening the joint. Also, vias too close to fine pitch devices can facilitate shorting if there is excessive solder dispensed. I have run many vias under fine pitch devices, just leave a bit of extra space if you can.

    As I mentioned, the ESD ring is not necessary, only desirable to protect the circuit from excessive handling. You would create a separate plane, then route it directly to the ground pin of your input to the supply. This is the star ground I referred to (assuming it isn't anywhere else).

    Where is the top plane's VCC source? I don't see it attached anywhere. As advised, you should also take the voltage regulator's output from the bulk capacitors, rather than the output of the regulator. So, the main vias under U5 and U6 should ideally be closer to C38 and C40. Those linear regulator packages are SOT-223s right? Are you sure the thicker pin is unconnected?

    Steve
     
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