Filters + PWM in place of DAC: Thoughts

Discussion in 'General Electronics Chat' started by Management, Feb 2, 2010.

  1. Management

    Thread Starter Active Member

    Sep 18, 2007
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    Please read ll before commenting. Thanks.

    The main driver for this conversation is the cost of a DAC versus using a PWM output and filtering to get what I want.

    What I want:

    1. To provide DC voltage level control to a driver circuit. Current methodology requires the utilization of a FPGA (so my hands are tied) that we thought we can use some DAC to provide digital control of the driver circuit.

    2. A second DAC is used to provide a sine wave another driver circuit from the I/O of the FPGA.

    I don't really want to talk about why there is a FPGA, there just is but to help me understand how I would go about a PWM design.

    I was thinking that for 1, if I wanted 2.5Vdc that I can have a PWM with mean value of 2.5V into a 25 Hz lowpass filter. Either way I would have a lowpass filter to get any DC component I want.

    Question is what order, 6th order. Can I do 4th order passive the 2 order active. Resistors are cheeapp ... like half a cent and caps can be 2 or 3 cents. One active device for something so simple can be 30-60 cents. Compared to a DAC there could be some serious cost savings. But what can I do to get 0.2% error in DC voltage from PWM to after the filter.

    For 2, I guess it would be a bandpass filter. What kind of approach can I take with this. All active. The PWM would probably be 50 MHz and I would want either 1.2 kHz or 2.2 kHz.

    Thoughts would be great in the questions and concerns above.

    EDIT: I have been reading this: http://focus.ti.com/lit/an/spraa88a/spraa88a.pdf
     
    Last edited: Feb 2, 2010
  2. Management

    Thread Starter Active Member

    Sep 18, 2007
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    I guess to start ... I would need to find a way to derive duty cycle resolution if I was using a 50 MHz cpu clock. The document talks about using clock counts but I am failing to see the relationship. I can choose the PWM cycle but don't know what to pick.

    Just want to have some governing equations for this. Any help would be great.
     
  3. MikeML

    AAC Fanatic!

    Oct 2, 2009
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    Even with a 50MHz FPGA, wouldn't the PWM be generated as n cycles HIGH and m cycles low, where m,n are multiples of 20n steps. Depending on how much resolution you need, m and n might be between 8 to 16bits. You tell me how much resolution you need, and I'll tell you how complex the filter needs to be :rolleyes:
     
  4. Management

    Thread Starter Active Member

    Sep 18, 2007
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    That easy?

    Ok well lets say I wanted 16 bit resolution. How complicated does my LPF have to be for 0.2% DC accuracy?

    Also, if you don't mind explaining how you came to that solution. I'd like to understand your line of reasoning.

    Thanks.

    EDIT: How good would a bandpass filter have to be to pick out both 1.2kHz & 2.2kHz and not get that harmonic of the 1.2kHz, i.e. 2.4 kHz? What order would you recommend?
     
    Last edited: Feb 2, 2010
  5. MikeML

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    Ok, to get 0.2% DC accuracy, that is 1 part in 500, so lets call it 1 part in 512, or 9 bits. Next, let's divide the 50MHz FPGA clock by 512, giving a frequency of 97656Hz (period of 10.24us). Use another 9 bit static register, the value of which will be how many cycles of the 9 bit counter will elapse before we switch a port pin high. You will need a parallel comparator to compare the counter value to the static value.

    The port pin will switch low as the 9 bit counter rolls from 511 to 0. This will produce a PWM signal were the low time is proportional to the value in the 9 bit register with a total period of 10.24us. The average level can be any where from 0/512 to 512/512.

    The next part of the task is to low pass filter the 97KHz PWM signal to get the average value. You didn't specify how long you are willing to wait for the output to settle to a new level after making a step change in the output. Basically, the shorter the time between updates, the more poles the filter has to have.
     
    Last edited: Feb 3, 2010
  6. Management

    Thread Starter Active Member

    Sep 18, 2007
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    Hey thanks a lot!

    Note: If I don't explain myself well please let me know and I'll rephrase. Thanks!

    Focusing on getting the DC component:

    I have 16-bit control of my PWM coming out of my FPGA. Now I have to filter it. Is there a relationship between the filtering and the number of bits? I'm starting to think there isn't that all I have to worrying about is getting rid of the ripple. Higher order filters get rid of more ripple. If I have 16 bit resolution on my duty cycle (subsequently the DC level) what higher order do I need, assuming there is a relationship? Would a 6th order be good?

    One thing I have to worry about is that I probably would need an active device 1st stage due to the high impedance I need upfront of the FPGA. Am I wrong in this assumption?

    Also, you brought up a good question as to how fast does I need this to change. I have to look into this but I think 6th order may be enough.
     
  7. MikeML

    AAC Fanatic!

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    You are missing a very important point. You have a PWM signal that repeats periodically. Say the period is 10.24us as in my example. That means the fundamental component is at 97.656KHz. The first thing we need to do is to suppress the ripple in the output. If there is only 9 bits of resolution, then we probably only need to suppress the ripple to less than 0.2%, call it 0.001 or 1/1000 which is -60db. So a lowpass filter that attenuates the fundamental by -60db would meet that requirement.

    A different requirement stems from how frequently you want to update the value at the output. Suppose you would settle for one new value per second. That means that you only need a filter that attenuates -60 db in five decades (100K to 1), or only 12 db per decade, which can be done with a single pole RC filter (-20db/decade).

    Now suppose you want to update the output 1000 times per sec, so now you have to get -60db worth of attenuation in only two decades (100K to 1K), so the filter has to be -60db/2decades or -30db/decade, which would be met by a 2 pole filter (actually -40db/decade).

    Now if you want a 16bit PWM, the fundamental frequency of the PWM will be only 50MHz/(2^16) = 763Hz. If you truly want 16 bits, then the ripple will have to be below 1/65536 or -96db. At a 1Hz update rate, that means you need -96db in under 3 decades (736 to 1), or -32db/decade, which you could meet with a 2 pole filter. At a 10Hz update rate, it would require -96db in only 2 decades which you could do with 4 poles.
     
  8. Management

    Thread Starter Active Member

    Sep 18, 2007
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    You are awesome. Thank you very much.

    Found out that the update rate is 25Hz. The 4 pole filter still applies if I need 16 bits resolution.

    I can do that with a 2-stage sallen-key or MFB lowpass configuration.
     
  9. Management

    Thread Starter Active Member

    Sep 18, 2007
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    For the second one,

    I need to get 1.2kHz and 2.2kHz tones from a separate PWM. Therefore, I would need a bandpass filter. I am concerned about 1.2kHz harmonic at 2.4kHz. I was thinking above using a Chebychev Bandpass to try and get the attenuation. I don't mind the ripple in the pass band but just wanted to get your take on how serious this bandpass has to be.

    Thanks again.
     
  10. MikeML

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    Are you trying to get the 1.2Khz and 2.2Khz at the same time? What are you trying to control on each one? Key it on/off? Vary the amplitude?
     
  11. Management

    Thread Starter Active Member

    Sep 18, 2007
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    Quick question, would a 25Hz LPF be good for the above?

    The FPGA would either output one or the other, via PWM, so I have to have a BPF capable of handling both.

    It (FPGA) would be AC coupled to the BPF. I only need the frequency and the FPGA is outputing a 16-bit sinewave via PWM.

    Don't understand what do you mean what I'm trying to control. I don't care about the amplitude ... just the frequency of the the two tones.

    Thanks.
     
  12. MikeML

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    So why not just use a variable modulus counter inside the FPGA to produce a 50% duty-cycle square wave at either 2.2KHz or 1.2Khz on one FPGA pin. To turn either of these into a sine-wave, use a low pass filter with a cutoff of ~2.5KHz. How many poles depends on how pure you want the sine wave.

    Starting from a square-wave, the first harmonic you have to knock down is the third harmonic, so at 3X1.2KHz = 3.6Khz, the attenuation needs to be Y db down, where Y depends on how pure. A complex filter that notches the third harmonic might be one way to go. Two band-pass filters centered on 1.2KHz and 2.2KHz might work, too.
     
    Last edited: Feb 4, 2010
  13. Management

    Thread Starter Active Member

    Sep 18, 2007
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    So I don't have to worry about the 2nd Harmonic for 1.2kHz when starting from a square wave?

    Also, thats how we do the sine wave with a 50% duty cycle PWM.

    The thing is I only have one pin for this on the FPGA so the tones have to come out of the same pin.

    I'll use a bandpass filter (Chebychev Type) but where can I center it?

    Does having 1.4kHz 3dB BW centered at 1.7kHz makes sense? 4-pole? Or should I just go for the LPF at 2.5kHz?

    The reason is because I can possibly use a 4 channel part that would be really cheap.

    Thanks again.
     
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