Here is another section of the "Bad Circuits" category from the book, "The Art of Electronics" by Horowitz and Hill.

I figured it would be a good idea to discuss various theories as to why each particular circuit would be deemed as a "Bad Circuit".

Starting off with figure A) from left to right,

i) This is a n-channel JEFT so with either 0V or 5V present at its gate the FET will be turned on. In other words,there will be no switching functionality at all since the output will be severely attenuated regardless on the control signal fed into the gate of the FET.

ii) In this configuration the body of the MOSFET should be tied to -15 volts in order to ensure that there is no forward bias across the channel-body junction. (Because the body forms a diode junction with the channel it must be held at a nonconducting voltage)

iii) Stumped, any ideas?

Figure B): \(G = 1000 = \frac{-g_{m}R_{D}}{1+g_{m}R_{s}}\)

\(\rightarrow g_{m} = -\frac{1}{20}\)

Assuming saturation,

\(I_{D} = k(V_{GS} - V_{T})^{2}\)

\(\rightarrow g_{m} = 2(kI_{D})^{\frac{1}{2}}\)

\(\rightarrow I_{D} = 4.526*10^{19}A!\) Which is a huge current! (Did I fudge something here?)

Figure C): Again JFET will be on regardless of its gate voltage. (i.e. ON for both 0V & 5V)

As for figure D) and E) I've run out of time for now, so I'll come back later and try to comment on those two as well.

What do you guys think?

Cheers!

 

For A (iii) I presume it's because the gate drain will short with the gate at +15V. Results in damage to FET.

For cct B one would need a much greater value than 10 ohms for Rs to achieve a good self bias condition.

 

For D, I would say that neither FET ever turns off so you have a short between Vdd and Vss.
For E, Q2 is never off and since there is very little resistance when Q1 is on, you have a short between Vdd and Vss.

 

For D, I would say that neither FET ever turns off so you have a short between Vdd and Vss.
For E, Q2 is never off and since there is very little resistance when Q1 is on, you have a short between Vdd and Vss.

For E), wouldn't Q2 always be off? For Q2, VGS = 0V regardless of the input on the top MOSFET, so it should be always turned off. Did I miss something?

Whether the top MOSFET Q1 is on or off would depend on the loading of the output node, right? Otherwise you can't figure out what the value of VGS for Q1 is.

 

Am I misunderstanding something in my last post?(i.e. post #4)

Would love for someone to comment.

Thanks again!

 

I totally agree with your comment you made in post 4.

 

I totally agree with your comment you made in post 4.

Good to know! Any other comments regarding any of the other circuits Jony130?