Hi all, thanks for taking a look at my post. As a hobby project, I am designing a simple 12VDC-5VDC power supply and am having trouble finding literature explaining how to implement compensation in the feedback loop at the error amplifier.

I have read chapters 7-9 of R.W. Erickson's "Fundamentals of Power Electronics 2nd Ed.", so I have a pretty good understanding of what type of frequency response I want the closed loop system to have and how to decide where to place the poles, zero, and inverted zero of a lead-lag compensator, but I cannot find much useful information on how to implement those features with a resistive/capacitive compensation network.

I did find the Texas Instruments released paper: "Designing Stable Control Loops" by Dan Mitchell and Bob Mammano ( http://www.ti.com/lit/ml/slup173/slup173.pdf ) and used the paper's guidelines for setting up a compensation network for a buck converter similar to the one I am working on. However, when I try to simulate it (I am using Simetrix 7.10), the feedback does not work if I have C2 populated. C2 is the capacitor placed in series with the feedback resistor of the error amplifier op amp. It is labeled C2 in the TI paper (p. 14) and the attached schematic print. I think the capacitor is blocking the DC feedback signal from making the full loop, but the TI paper explicitly shows it in that location of the network.

If anyone could expalain to me how to physically implement a compensation network (preferably of a lead-lag or PID controller type) or where to find information on the topic, I would greatly appreciate the help. Thank you!

 

I have used the information in that TI reference to successfully design a buck regulator so I'm not sure why your circuit does not work with the capacitor. What switching frequency are you using? What are the symptoms of the failure?

The capacitor in the feedback loop is the lag portion (integrator) of the feedback which gives zero output error when the loop is in steady-state balance. This is to give the best regulator error. You can operate with just resistive feedback but that will give you some error in the regulated voltage (as determined by the loop gain).

 

Hi crutschow, thanks for the reply. I have attached two pdf prints of the output voltage waveform in the simulation - one with C2 populated, one without. The difference seems most indicative of the symptoms that C2 causes.

I am using a 100kHz switching frequency.

 

I'm trying to simulate your circuit. I assume V4 is a sawtooth or triangular wave. What is it's amplitude?

 

It is a sawtooth waveform. V4_min = -0.5V, V4_max = 3.5V

I am using a UC2573, so that's where I got the V4 characteristic and the Vref = 1.5V value.

 

Below is my simulation of your circuit using LTspice (free program) with the feedback capacitor in the loop. I did find that the circuit was marginally stable so I increased the value of the feedback capacitor (C4 on my circuit) from 6nF to 9nF which helped. You might want to go even larger for better phase margin such as 15nF or so.

To check the stability you can input a step function on the reference voltage (V6 in my circuit). For example a step from 1.5V to 1.7V when it has reached steady-state after the start-up will give a step in the output voltage. If the loop is stable it will settle to the new value with little or no ringing.

I also reduced the value of the sense resistors (R5 and R6 on my circuit) by a factor of 10 in my simulation since the high values you used would cause a significant voltage error due to the loading by the input resistor (R7 on my circuit).

Note the significant startup overshoot, which the UC2573 should minimize with it's current-limit capability.


View attachment Buck Reg Simple.asc

 

Wow, thank you! I guess it is time to start using LTSpice again. I started using Simetrix (also free for the intro version) on a recommendation, but it seems to have failed me here. Is it simple to do an AC sweep analysis on LTSpice? I would be interested in checking that out.

And in reference to the sensor resistors, can you explain the term 'loading'? Do you mean that current would be forced into the input resistor because of the high values of the sensor resistors?

Also, it should be possible to reduce that initial spike by improving the damping factor, right? Or does that have a limited effect?

Thanks again for the help!

 

Yes, you can do AC analysis, but only for linear circuits. You can't do that for the buck regulator unless you convert the PWM generator circuit to a linear equivalent. I can show you how to do that, if you like.

The R13 input resistor takes signal current to operate the op amp since R13 goes to the virtual ground of the op amp (sitting here at 1.5Vdc). This current must be supplied by R5 and R6, which will cause a voltage drop, due to their equivalent Thevenin resistance (105kΩ). You basically have a voltage divider between this 105kΩ equivalent resistance and the 3.38kΩ value of R13. So you want the Thevenin value of R5 and R6 to be less than the value of R13 for minimum error due to the signal current. (Actually 3.5kΩ and 1.5kΩ would be even better than the values I used).

It's a startup transient that's basically a result of the resonance of the output inductor and capacitor. You can't change the damping of that without adversely affecting the operation of the circuit. The problem is that the control signal at the PWM comparator X2 is a zero volts at startup and that is the condition for 100% maximum duty cycle. Thus the switch S1 is fully turned on until the feedback loop can take control, which takes a couple ms, due to the feedback time constants.

If you remove op amp X1, feed the output of op amp X3 directly the the plus input of the comparator X2 (with the sawtooth signal connected to the minus input), then the polarity of the signal is reversed so that the duty-cycle is zero instead of 100% at startup. Then you add a RC delay of about a ms time-constant to the reference V7 to bring the voltage up slowly. This will prevent the overshoot. See below for the simulation.

 

I recalculated the compensation values from the TI reference and the only difference I found from your values was that C2 should be 55nF, not 6nF.

 

Below is an AC simulation of the open-loop response of the circuit to give a Bode plot, similar to that shown in the TI reference.

To perform AC simulation you must substitute a linear gain block (EPWM) for the switching PWM modulator portion of the circuit with gain equal to the equivalent gain of modulator. (15V/4V = 3.75).

 

I had C2 as 6nF, so I am thinking I made an order of magnitude error. Thank you for catching that. And thanks for showing me the linearization of the PWM block/AC analysis. That will definitely be useful and interesting to perturbed and see the effects.

Unfortunately, The UC2573 does not allow me to input to the non-inverting signal of the error amplifier or to connect a time constant as shown to the reference voltage. But I am thinking the current limit function could provide the same function.

I will double check my calculations and make sure there are not any more simple errors. Thanks again for all the help so far.

 

According to my simulations the best AC phase margin and minimum transient overshoot/ringing occurs when C2 is ≈60nF and C4 is ≈10nF.

 

Great! Thank you. This is all very helpful. When you generate the Bode plot for the open loop response like that, is that the plot I would base my compensator values on? I seem to remember that the closed loop response is important.

 

Both closed-loop and open-loop responses are important but they are related. Good gain and phase margin in the open-loop Bode plot generally means good closed-loop transient response. A poor margin generally results in large overshoot and ringing in the closed-loop response. It's usually easier to fine tune the compensation values with the Bode plot since it's easier to see the effect of small changes in the values, as compared to the transient response.

In the Bode plot the main concern is usually the phase margin at the 0dB gain point. You want that to be 45° or more if possible. That's approximately what I got in simulations with the values in Post #12.

 

I see. Then my confusion was that I thought the phase margin in the closed loop Bode plot was what predicted ringing and overshoot.

 

The closed-loop response masks the effect of the various loop time-constants due to the feedback around the loop. The open-loop response shows the effects of all the loop time-constants and thus can more readily predict the behavior of the closed-loop response.

 

Noted. Thank you. I was able to put together a model and do an AC sweep analysis with some realistic part values and got a phase margin near 45 degrees. Next, I want to implement the current limit function of the UC2573 but I am having trouble getting LTSpice to do what I want. It seems there is a problem in the AND gate I am using. Any suggestions?

 

I ran the simulation again and found that it is just running extremely slowly. It seems to be working, though. I think I will just assemble the circuit and test it out. Thanks for all the double checking on the compensation stuff and the explanation of open vs. closed loop AC analysis.