Feedback Compensation in SMPS

Thread Starter

Fethiyeli

Joined Mar 16, 2013
34
Hi, i would like to ask about feedback compensation. How do u get the bode plot that is needed for feedback compensation ? We have two choices as i know, one of them is to use network analyser and second one is simulations. I am using Orcad and PSIM for SMPS but it is almost impossible to get bode plot. Is there any easier way to get bode plot ? I would like to implement feedback compensation network correctly but i dont know how to do it. I have read some SMPS textbooks but it always say that bode plot is needed for the circuit.
 

tindel

Joined Sep 16, 2012
936
Some of the guys at work break the loop using a high-bandwidth op-amp (Av=1) to inject a sine wave into the loop and see it go through the loop. It's a little more of a pain to do it this way circuitry wise, but it takes out the question of low-frequency effects. I prefer the transformer/resistor method at this point... it's just easier for me. I've yet to actually use the op-amp method though... so maybe I'll change my mind once I do it that way.
 

tindel

Joined Sep 16, 2012
936
Another thing to point out - you should NEVER depend on a spice analysis to verify your loop stability... in fact you should verify your stability at each stage of development. I was reading a story when I was researching this a while back about a guy that was having problems with the production build of his SMPS failing. He took stability plots of the production run and they were vastly different than the prototype he had developed. The culprit? A bean-counter decided to take out the tape between the primary and secondary windings of the transformer.

I'm fortunate to have a venible at work... these days they are pretty cheap... get one if you plan on doing this a lot.
http://venable.biz/products/frequency-response-analyzers/

PS... I'd be shocked if anyone anyone has a real need for anything over 5MHz versions... I've heard of a couple switchers at 1MHz, but never 50MHz... your cross-over frequency should at least be 1/10 of the switching frequency.
 

bountyhunter

Joined Sep 7, 2009
2,512
Another thing to point out - you should NEVER depend on a spice analysis to verify your loop stability...
That should be engraved into the forehead of every EE student in his freshman year.

I was at National Semi in 2008 and they hired a super-duper hot shot designer to come in and develop a new linear regulator tagged the LP38501 which was going to be GUARANTEED to be stable with any kind of input or output capacitor. Hence the name of the product line was going to be "Flexcap".... the name "Anycap" had already been trademerked by our competitor.

The part was finished and set for release, the design group had "verified" performance and the ad copy was already at the magazines for publication..... Of course, I was checking the part on the bench as I always did to make sure it was OK when I discovered it was not stable with any cap. In fact, there was a range of input caps where it oscillated like a screaming banshee.

I ran nto the designer's office and told him the problem which he refused to believe.... so I made him walk to the lab (someplace he had probably never been before) and witness the problem. He curled his face up as if smelling a rotten egg and admitted that it seemed to be a problem.

Then the good part:

ME: "I have a stack of data from you showing that the part was stable under these conditions. Didn't you test the part?"

HIM: "We ran simulations for all of those values and it worked fine."

I just stared and tried very hard not to say what I was thinking......

So we had to recall the ad copy and rush new (corrected) copy over the day before going to print.

And the LP38501 data sheet still contains the info warning about the problem I found bench testing the day before release:

http://www.ti.com/lit/ds/symlink/lp38501-adj.pdf

To ensure proper loop operation, the ESR of the capacitor used
for CIN must not exceed 0.5 Ohms.
Which means it is NOT stable with any cap, just the ones that have very low ESR. Tens of millions of dollars could have been burned thanks to an idiot who worships at the simulation altar.... as Maxwell Smart used to say: "Missed it by THAT much!"
 
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Thread Starter

Fethiyeli

Joined Mar 16, 2013
34
I calculated the output inductor and capacitor according to pressman's book but when i put calculated inductor and capacitor, the graph of output is like that:





I've tried many things but nothing has changed. Output voltage is always so low. I would like to have 370VDC at output. There are two problems, i can not able to get 370VDC at output and other one is output inductor and capacitor do not behave as expected. I mean ripple, CCM etc.
 

bountyhunter

Joined Sep 7, 2009
2,512
Could anyone answer my last question ? =)
It was:

I've tried many things but nothing has changed. Output voltage is always so low. I would like to have 370VDC at output. There are two problems, i can not able to get 370VDC at output and other one is output inductor and capacitor do not behave as expected. I mean ripple, CCM etc.
Here's the answer: NO I don't know the answer and I spent 20 years designing switchers. I don't know the characteristics of any of the components (cap ESR, inductor saturation current, etc) so I have no idea why the circuit doesn't work.

I also have no idea why you posted the voltage after only five milliseconds since it takes a switcher much longer than that to start up.
 

Thread Starter

Fethiyeli

Joined Mar 16, 2013
34
Yes you're right. When i set the simulation time to 1s, i got about 290VDC at output but i am still far to get 370VDC. I think i have feedback problem. Duty cycle did not change over time simulation time. I put resistive load and thats why voltage and current waveforms are same but inductor current is discontinous. It was supposed to be continous according to calculation. Thnx.
 
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