Fast Level Translator Driving into 50 ohms.

Discussion in 'General Electronics Chat' started by davycampbell, Jun 11, 2010.

  1. davycampbell

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    Jul 10, 2009
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    I am trying to drive a 5ns wide pulse of variable frequency up to 100MHz into a 50 ohm load & achieve a signal level of at least 3.5V. The rise & fall times of the pulse have to be in the reion of 1ns.
    The source of my signal is taken from the output of an FPGA and has a guaranteed Voh of 2.4V.

    I currently have an NXP 74F3037 NAND driver connected to the output of the FPGA & I am getting a pulse of approx. 3V but the rise time is disappointing (3ns).

    Does anyone have any suggestions as to how I could achieve this, either with discrete components or using a translation IC (I have looked at level translating ICs but have struggled to find one that handle the speed & pulse width).

    Thanks
     
  2. SgtWookie

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    Jul 17, 2007
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    What does your circuit board layout look like?

    Are you using the DIP-16 or SOT-162 package?

    What are you using for bypass caps for the 74F3037?
    Do you have them directly across the VCC and GND pins?

    A straight piece of wire 10mm long has roughly 15nH inductance. It adds up very quickly.

    Multilayer ceramic caps have quite a bit of parasitic inductance. It's not obvious at low frequencies, but when you're getting into the 500MHz range, the parasitics have quite an effect. You may need to use single-layer caps.

    Just a reminder that an ideal square wave is the sum of the fundamental frequency, plus all of the odd harmonics of the fundamental frequency. If you want a halfway decent output signal, you'll need at least 1GHz bandwidth. That's not easy to do.
     
  3. nsaspook

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    Aug 27, 2009
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    Take a look at this. www.potatosemi.com/datasheet/PO49FCT3802A.pdf
    http://www.ibselectronics.com/active/potato_semiconductor_a_1.htm
     
  4. davycampbell

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    Jul 10, 2009
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    Thanks for the replies.

    The package used is the SOT-162.

    The bypass caps are 100nf Murata monolithic ceramic GRM155F51E104ZA01D, there are 2 of these (one for each Vcc pin). There is also a 10uF Panasonic electrolytic EEE-FK1C100R.

    The traces from the bypass caps to the pins are very short, only a few mm.

    One problem might be that the +5V power (Vcc) does not come directly from the 5V plave but from a 200mm long, 2mm thick trace taken from the plane. I have attached a picture of the power trace.

    [​IMG]
     
  5. Ron H

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    Do the bypass caps return directly to the GND plane?
     
  6. SgtWookie

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    I exported your image from Word so that it can be viewed without any extra software. .PNG image attachments are preferred; they are compact and load very quickly.

    It's kind of hard to tell from the board image, but do you have lots of decoupling caps between the power and ground planes, at least every inch? Are the decoupling caps the same as you're using on the IC in question?

    Can you highlight the traces where the input and output signals are coming from/going to?

    Might sound like we're asking lots of questions, but at those kinds of speeds, you need oodles of bandwidth. Parasitic capacitance and inductance will really wreak havoc with your signals.
     
  7. Ron H

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  8. davycampbell

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    Jul 10, 2009
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    I don't have decoupling caps every inch, only at the IC.
    The decoupling caps at the IC do return directly to gnd.

    I have added some some traces:

    1. 5V Trace
    The 5V supply trace is highlighted in pink. The 5V supply is taken from an AC/DC converter (external to the board) & comes into the board in the top left corner wher it is filtered. Ideally I would have a 5V plane covering the whole board but this was not implemented as 5V is not widely used on the board & other more widely used voltage rails were implemented on planes (1.2V, 2.5V & 3.3V)

    2. 5V Trace Zoomed
    The 5V supply is again highlighted in pink & is shown where it connects to the 74F3037 on pins 12 & 13. The 3 x bypass capacitors are also highlighted in pink. The ground plane is highlighted in white.

    3. I/O Top of Board
    Input to the 74F3037 is on pin 2, the output is on pin 3

    3. I/O Bottom of Board
    Traces that connect to the I/O pins are highlighted, the IC outline is overlayed.

    Thanks again for your help.
     
  9. Ron H

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    Davy, what makes you think the 74F3037 will ever attain 1ns rise and fall times, even with a perfect layout and no load?I realize that this can be construed as a negative comment, and negative comments are sometimes frowned on unless accompanied by suggestions for a solution. Unfortunately, I don't have any other than that proposed by nsaspook.
    I just don't want to see you beating your head against the wall, trying to turn a sow's ear into a silk purse.
     
    Last edited: Jun 16, 2010
  10. Papabravo

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    There is a related thread where a guy wants to measure sub nanosecond intervals. I pointed out to him, and I'll replicate the comment for your benefit. I don't know of any discrete logic family that will achieve what you want at those voltage levels. If you think about it 3.5 V into 50 Ohms requires 70 mA which is in excess of most discrete parts out there. I suggested to our friend that flip-flops clocked in excess of 1 GHz. might be found in a CMOS FPGA with a low voltage core. I'm pretty sure that won't help you a bit.

    Last item is that parasitic capacitance and inductance will absolutely kill you at those frequencies. If you have the stones for it, some microstripline design with some MMIC's might get you where you need to be. These designs are not cheap in terms of part cost and test equipment to verify proper operation. The cost of the CAD tools alone will absolutely flatten your wallet.
     
  11. SgtWookie

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    Actually, HP's AppCad is freeware. It has some handy tools for calculating things such as micro stripline, etc.

    Download page is here:
    http://www.hp.woodshot.com/

    Still, like PapaBravo suggests, whipping up a design in software and actually getting it to work in hardware will be quite a challenge. Even a minor change of board material or thickness will throw all of your work out the window.

    I really don't know what the source impedance of an NXP 74F3037 NAND driver is; but if it's not matched to the load you'll have big problems.

    You might luck out and find a used network analyzer with an S-parameter test set that's been through calibration and can sweep through a couple GHz for around $10k, but prices for new equipment like that go into the nosebleed category. Just annual calibration costs will easily top five grand.
     
  12. Papabravo

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    It is true that AppCAD is a freeware download. I found it interesting if somewhat limited. Of course after you use the expensive tools anything less is kinda a PITA. I would be interested to hear if any noobs out there have actually used AppCAd for useful design work. I guess if you're an expert and you found it useful I'd be interested in hearing about that too.
     
  13. SgtWookie

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    I didn't mean to imply that AppCad was any kind of end-all be-all tool; but it's useful if you don't have boatloads of cash to drop on something better.

    Even IF you have the high-end tools, you will still need a network analyzer to really see what's going on.
     
  14. davycampbell

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    Jul 10, 2009
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    As I mentioned in the original post I am trying to drive a 5ns wide pulse of variable frequency up to 100MHz into 50ohms.

    A rise time of 1ns would be nice but I can live with 2ns.

    I have attached a an oscilloscope plot which shows the output (green trace) that I currently have. This was measured using a 1.5GHz active probe. The repetition frequency was set to 80MHz for this measurement but the rising edge exhibits the same characteristics at 100MHz. The yellow trace shows the voltage at the Vcc pin but this was measured using a standard 500MHz scope probe.

    The slope of the rising edge is fast enough until it reaches 1V but then it slows down and exhibits a pronounced 'bump'. If the initial slope was continued until the output reached its maximum level (> 3V) the overall rise time would be approx. 1.5ns which would be acceptable. The 'bump' corresponds to dip in the voltage measured at one of the 5V Vcc pins on the 74F3037.

    The second plot shows the Vcc pin measured with an Active FET probe, the dip at the Vcc pin corresponds to the 'bump' in the output.

    I am now thinking that the 74F3037 could give me the output that I am looking for & that my power supply (layout) is the issue.
     
  15. Papabravo

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    The shape is quite typical of charging the frequency dependent gate capacitance of a MOSFET. There are few really good solutions that you can try at those frequencies. A MOSFET gate driver may provide some insight into doing a discrete driver, but this will still be a challenge.
     
  16. Ron H

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    The waveform could also be indicative of a transmission line reflection, which only apperas on one edge due to the source impedance being different for pull up than it is for pull down.

    EDIT: Or maybe not. I can't come up with a simulation of that waveform.

    The more important measurement is at the destination. Can you post that waveform?
     
    Last edited: Jun 17, 2010
  17. davycampbell

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    Jul 10, 2009
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    The waveform at the destination (A 1GHz scope with the 50 ohm input termination selected) is pretty much identical to the waveform that I have already posted. The cable used to connect the pcb to the oscilloscope is a 100cm long RG-174 coax.
     
  18. SgtWookie

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    The rising edge hesitation sure looks like Miller effect. I don't know offhand why it's not showing on the falling edge.
     
  19. Ron H

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    Is the load on this pin the gate of a MOSFET?
     
  20. Papabravo

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    Well if it is it would be pretty hard to claim that the load had an impedance of 50 Ohms. There might be a resistive terminator there, but that hardly qualifies if it's in parallel with the gate of a MOSFET.
     
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