# Exceedingly Simple XOR Gate

Discussion in 'General Electronics Chat' started by IsquaredC, Mar 3, 2012.

1. ### IsquaredC Thread Starter New Member

Nov 28, 2011
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I've always been facinated with the concept of minimization in electronics, whether it's simplifying things like Boolean expressions or finding new ways to reduce component #'s in integrated circuit designs. I tried to apply these minimization techniques on a relatively component-heavy logic gate (XOR gate) and this is what I came up with (Thumbnail below). All-in-all, it uses four diodes, two resistors, and one PNP transistor. (Which I assume makes this a DTL circuit). This circuit uses a rectifier to separate the A and B inputs when one is zero and the other is one to allow current to pass through the base of the transistor, changing Q to 1. Are there even simpler XOR gate designs out there? And also, are rectifiers typically used in digital logic circuits or are they more exclusively used for rectifiying AC in things like power supplies?

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2. ### Ron H AAC Fanatic!

Apr 14, 2005
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Here is a 3 transistor XOR. It is probably best implemented inside an IC.

3. ### hobbyist Distinguished Member

Aug 10, 2008
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Your circuit looks good, and will work properly.

However one note about it, the strength of the output current is the direct result of the input current through the diode and PNP transistor.

This could cause eratic behavior, it is best to keep the outputs and inputs currents seperate from eachother.
So the output is consistent in current flow regardless how big or small the input signal strength is.

Here is one solution, to that kind of dilemna.
Better solutions would involve more components for even better stability.

In actuality the 2 inputs should have pull down resistors to ground as also.

Yes diodes are used in digital circuitry as well as rectifiers in analog circuits.

Digital circuits they are refered as steering diodes.

Last edited: Mar 4, 2012
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4. ### blondiepassesby New Member

Mar 23, 2014
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OP has also been presented here:

http://www.edn.com/design/other/437...function-with-a-diode-bridge-and-a-transistor

Nice idea in general, but beside the fact that there's no buffering (as pointed out
above), the circuit as presented has another problem: it only works well a low speed.

Around 20KHz, the PNP can't switch off fast enough and all the signal throughs
are lost.

The problem is even worse in the third solution presented.

5. ### blondiepassesby New Member

Mar 23, 2014
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Here's an LTSpice sim with a 2N3906 that highlights the problem at ~20kHz.
At 100kHz, the trough disappear completely.

6. ### crutschow Expert

Mar 14, 2008
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Ron, that link doesn't work for me.
Edit: Never mind, I found the circuit shown below.

Last edited: Jan 1, 2017
7. ### DickCappels Moderator

Aug 21, 2008
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You deserve a prize for originality.

8. ### Robin Mitchell Well-Known Member

Oct 25, 2009
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@crutschow If A is 1 and B is 0 wont the output sink to ground? M1 would be on as VG > VS and M1 is connected to M3 which is also on.

9. ### crutschow Expert

Mar 14, 2008
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True. I didn't look at its operation closely when I posted.
The circuit is proposed here, but off-hand I don't see how it can work.

10. ### Jony130 AAC Fanatic!

Feb 17, 2009
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Here you can read how this circuit work
http://waset.org/publications/1588/...der-design-using-novel-3-transistor-xor-gates

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Mar 14, 2008
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Feb 17, 2009
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No it isn't.

13. ### crutschow Expert

Mar 14, 2008
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My apologies.
It looked the same at first glance due to the similar titles.

So apparently it works because of some particular adjustment of the threshold voltages and W/L ratios on the IC.
It won't work with discrete transistors.

Dec 19, 2007
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15. ### WBahn Moderator

Mar 31, 2012
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That circuit has a few problems.

If A is HI and B is LO, then output should be HI. But even with B LO, the inverter is pulling the output hard to ground via M1. So at the very least you have contention at Y between M1 and M3, which is presumably why M3 is 5x as wide as M1.

If both A and B are LO, then the output should be LO, but there isn't anything that is strongly doing this. You are trying to pull Y down using a PFET and so you will have a hard time pulling Y down much below the threshold voltage.

This design also couples the output back to the input, which is asking for trouble.

We used a version of an XOR gate that used transmission gates, but found that the resulting coupling between input and output was a disaster in the making and so changed to a fully CMOS implementation (and by CMOS I mean a complementary design in which the pull-up logic was the complement of the pull-down logic) with the resulting design containing 12 transistors. We never had reason to regret, though on some designs we moved the input signal inverters out of the XOR gate and shared them amongst many blocks that needed complementary input signals.