Exam Revision help.

Discussion in 'Homework Help' started by skillz, Mar 16, 2008.

  1. skillz

    Thread Starter New Member

    Mar 16, 2008
    4
    0
    hi,

    im wondering if anyone can help me with a revision problem i have...

    I understand the difference between
    synchronus = everything happens in time with the clock.
    Asynchronus = is it happens in time with the inputs.

    Therefore i need to create an Asynchronous circuit that have 2 inputs
    O(oscilation) and G(gate)
    and one output Z.

    O which is normaly low recieves a series of variable frequency and variable length (TTL pulses) which, under the control of G, are to be copied as accuratley as possible in length to the normaly low output of Z

    i need to do this using SR flip-flops and standard gates that meets the specification for a gated clock circuit.

    Thanks in advance for any help.
     
  2. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
    282
    Apply G (high) to one input of a dual input AND gate. Looks like the output will then follow O pretty faithfully.

    Am I missing something?
     
  3. skillz

    Thread Starter New Member

    Mar 16, 2008
    4
    0
    so draw out the circuit i would have something like an

    AND2 gate leading into a SRflip-flop

    But surely thats not sufficient to represent a gated clock circuit?

    if O is high when G is asserted then Z does not first go high until the beginning of the next input pulse

    each assertion of G must result in two pulses copied to Z

    And finally an assertion of G is not active if it occurs before the output is complete from the previous active assertion

    Therefore how would the circuit diagram for that look like?
     
  4. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
    282
    That was not implicit in your first post - "Therefore i need to create an Asynchronous circuit that have 2 inputs
    O(oscilation) and G(gate)
    and one output Z"

    An AND gate satisfies those conditions.

    Can you post up a truth table? That will help in figuring out what needs to happen.
     
  5. skillz

    Thread Starter New Member

    Mar 16, 2008
    4
    0
    SR flip flop

    S R Action
    0 0 Restricted
    0 1 Q = 0
    1 0 Q+ = 1
    1 1 keepstate

    hope this enough to make sense?

    also:

    S R Q+
    0 0 Keep state
    0 1 0
    1 0 1
    1 1 Avoid
     
  6. skillz

    Thread Starter New Member

    Mar 16, 2008
    4
    0
    can anyone assist??
     
  7. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
    282
    Those are truth tables for S-R flip-flops. It would be helpful to have you explainwhy the Z output can't be the output of an AND gate. What purpose do the flip-flops serve? How is it that each assertion of G must have two pulses to Z? If Z is not an output of a gate, what is it?

    Your assertion - "Therefore i need to create an Asynchronous circuit that have 2 inputs
    O(oscilation) and G(gate)
    and one output Z" does not involve anything more than one standard gate to be mechanized.
     
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