evaluation

Discussion in 'Homework Help' started by renegadegas, May 9, 2013.

  1. renegadegas

    Thread Starter Member

    Dec 2, 2012
    89
    0
    Hello,

    Can someone please give me some tips on how to evaluate a full adder circuit designed using NOT, AND and OR Gates and another full adder circuit designed with NAND GATES only.

    I appreciate your help.

    Thank you.
     
  2. WBahn

    Moderator

    Mar 31, 2012
    17,757
    4,800
    What do you mean by "evaluate"? An evaluation needs to be against a set of metrics. Some that might apply here are speed, area, cost, etc. Which metrics you are evaluating will dictate HOW you evaluate against that metric.
     
  3. renegadegas

    Thread Starter Member

    Dec 2, 2012
    89
    0
    Thanks for replying Mbahn,

    I know having fewer chips reduces the overall cost of the circuit, having less inputs on the logic gates improves the performance and the chips heating up, but i'm guessing the NAND adder circuit would perform much better than the normal full adder circuit because the same chip has been used.

    I have attached the circuits i designed.

    The NAND adder circuit has 6 more chips than the the original circuit. Would this
    work faster than the original circuit?. Would this consume less energy? Would this cost less to manufacture although it has 6 more chips than the original circuit built with the AND, OR and NOT gates?.

    Thanks for reading.
    You have been very helpful.
     
  4. WBahn

    Moderator

    Mar 31, 2012
    17,757
    4,800
    What do you mean by "chips"? If you are using SSI logic (such as 74xx or 40xx) then you would need to take into account the fact that most of the two-input gates are four gates per package and inverters are typically six per package.

    You will also want to look at the delays. Typically AND and OR gates have about twice the propagation delay of NOT, NAND, and NOR gates. But some manufacturers artificially slow down the faster gates to make them balanced and even most that don't spec the performance limits based on the slower gates.

    Your NAND-based design uses 26 NAND gates. It can be done with only 11.
     
  5. renegadegas

    Thread Starter Member

    Dec 2, 2012
    89
    0
    My reference to chip was the logic gate.

    Im surprised about your assertion on the possible use of 11 NAND gates because
    we've been instructed to use only 2 input NANDS. The circuit would workout
    cheaper if that is possible, it would work faster and consume less energy as well.
    I'll be having a look at it again. Because i have already removed
    the unnecessary nands .

    Any tips on how to further reduce the the NAND gates?
     
    Last edited: May 10, 2013
  6. WBahn

    Moderator

    Mar 31, 2012
    17,757
    4,800
    Keep in mind that you can make an XOR with four 2-input NANDs. Then think of the POS stock implementation and remember this little theorem by a guy named DeMorgan.
     
    renegadegas likes this.
  7. renegadegas

    Thread Starter Member

    Dec 2, 2012
    89
    0
    Thanks for the advice.

    i'll research on that and get back to you.

    Do you ever sleep?. You are always here.
     
    Last edited: May 10, 2013
  8. renegadegas

    Thread Starter Member

    Dec 2, 2012
    89
    0
    thaks MBahn.
    i figured out your advice on the XOR.
    I have also gone back to read the instructions for my assignment and
    we were restricted to only using OR, AND and NAND gates but i'll be mentioning
    the use of XOR during my evaluation as i reckon that will make the circuit work faster
    and it would be cheaper and also simplify the circuit.

    Thanks again
     
  9. WBahn

    Moderator

    Mar 31, 2012
    17,757
    4,800
    You're welcome. And, as I pointed out, once you know how to do it with an XOR, you can trivially replace each XOR with four 2-input NAND gates.
     
    renegadegas likes this.
Loading...