ERROR in VHDL Code for FPGA(Spartan 3E) implementation of AES

Discussion in 'Programmer's Corner' started by sakshi aneja, Mar 5, 2012.

  1. sakshi aneja

    Thread Starter New Member

    Mar 5, 2012
    1
    0
    This error is coming in our VHDL program code simulated in Xilinx 13.1
    Please suggest a possible solution for this as soon as possible.I am enclosing the top module of my code in brackets


    ERROR:pack:1107 - Pack was unable to combine the symbols listed below into a single IOB component because the site type selected is not compatible. The
    component type is determined by the types of logic and the properties and
    configuration of the logic it contains. In this case an IO component of type
    IOB was chosen because the IO contains symbols and/or properties consistent with output or bi-directional usage and contains no other symbols or properties that require a more specific IO component type. Please double
    check that the types of logic elements and all of their relevant properties
    and configuration options are compatible with the physical site type of the
    constraint
    Code ( (Unknown Language)):
    1.  
    2. (
    3. -- 128bit AES Encryption Implementation
    4. -- Contains device_level includes uController and Memory
    5. -- Filename: device_level.vhd
    6. library ieee;
    7. use ieee.std_logic_1164.all;
    8. use work.global.all;
    9.  
    10. entity DEVICELEVEL is
    11.      port(  
    12.            clk:in std_logic;
    13.            resetn:in std_logic;
    14.             --ps2 keyboard
    15.            ps2_data: inout std_logic;
    16.            ps2_clk: inout std_logic;
    17.             -- lcd
    18.            display_out: out std_logic_vector(7 downto 0);
    19.            nlcd_ena : out std_logic;
    20.     --      loaddata: in std_logic;
    21.  --        loadencrypt: in std_logic;
    22. --         loadkey : in std_logic;
    23.           lcd_rw :out std_logic;
    24.           lcd_rs : out std_logic;
    25.             -- LED ASCII Keypress
    26.            leds: out std_logic_vector(7 downto 0));
    27. end DEVICELEVEL;
    28.  
    29. architecture int_structure of DEVICELEVEL is
    30.  signal     device_address_bus: std_logic_vector(10 downto 0);
    31.  signal     device_rom_bus: std_logic_vector(7 downto 0);
    32.  signal     device_ram_bus: std_logic_vector(15 downto 0);
    33.  signal     device_opcode: std_logic_vector(3 downto 0);
    34.  signal     device_status: std_logic_vector(2 downto 0);
    35.  signal     inverse: std_logic;
    36.  signal     int_loaddata,int_loadencrypt: std_logic;
    37.  signal     rx_read, rx_data_ready, rx_released : std_logic;
    38.  signal     rx_ascii : std_logic_vector(7 downto 0);
    39.  signal     intLCD2Core : integer range 0 to 15;
    40.  signal     Core2LCD : std_logic_vector(7 downto 0);
    41.  signal     asciimode,inputaccept: std_logic;
    42.  signal     loaddata,loadencrypt,loadkey:std_logic;
    43.  signal     keypress: std_logic;
    44.  
    45. begin
    46.  int_loaddata    <=  not loaddata    and inputaccept;
    47.  int_loadencrypt <=  not loadencrypt and inputaccept;
    48.  
    49. CORE: AESCORE port map (opcode=>device_opcode,
    50.                         inverse=>inverse,
    51.                            rombus=>device_rom_bus,
    52.                           rambus=>device_ram_bus,
    53.                            status_ext=>device_status,
    54.                         address=>device_address_bus,
    55.                             reset=>resetn,
    56.                            clk=>clk,
    57.                            rx_read=>rx_read,
    58.                             rx_data_ready=>rx_data_ready,
    59.                            rx_ascii=>rx_ascii,
    60.                            rx_released=>rx_released,
    61.                                 inputaccept=>inputaccept,
    62.                                 asciimode=>asciimode,
    63.                            leds  => leds,
    64.                                 loaddata=>loaddata,
    65.                                 loadkey=>loadkey,
    66.                                 loadencrypt=>loadencrypt,
    67.                             intLCD2Core=>intLCD2Core,
    68.                             Core2LCD=>Core2LCD);
    69.                        
    70.  
    71. CODE: PRGRMCNTRL port map (
    72.                        status=>device_status,
    73.                     reset=>resetn,
    74.                       clk=>clk,
    75.                     loadkey=>'0',
    76.                     loaddata=>int_loaddata,
    77.                     loadencrypt=>int_loadencrypt,
    78.                     inverse=>inverse,
    79.                       opcode=>device_opcode);  
    80.                                                        
    81. ROM: SBOX_ROM port map (
    82.                       address=>device_address_bus(7 downto 0),
    83.                           clk=>clk,
    84.                       read=>device_address_bus(10),
    85.                       inverse=>inverse,
    86.                       output=>device_rom_bus);
    87.  
    88. RAM: KEY_RAM port map (
    89.                       address=>device_address_bus(6 downto 0),
    90.                         iobus=>device_ram_bus,
    91.                           clk=>clk,
    92.                         read=>device_address_bus(9),
    93.                     write=>device_address_bus(8),
    94.                         enable=>resetn);
    95.  
    96. PS2: ps2_keyboard_interface
    97.   port map(
    98.        clk => clk,
    99.        resetn  =>resetn,
    100.        ps2_clk => ps2_clk,
    101.        ps2_data=>ps2_data,
    102.       rx_data_ready=>rx_data_ready,
    103.       rx_read=>rx_read,
    104.       rx_ascii=>rx_ascii,
    105.       rx_released=>rx_released,
    106.        asciimode=>asciimode
    107.      );
    108.  
    109. LCD: LCD_top port map (
    110.              clk => clk,
    111.              reset => resetn,
    112.              display_out=>display_out,
    113.              nlcd_ena =>nlcd_ena,
    114.               lcd_rw => lcd_rw,
    115.              lcd_rs =>lcd_rs,
    116.             opcode => device_opcode,
    117.            asciimode => asciimode,
    118.            keypress => rx_data_ready ,
    119.             inputaccept=>inputaccept,
    120.                intLCD2Core=>intLCD2Core,
    121.                Core2LCD=>Core2LCD );
    122.  
    123.  
    124.  
    125. end int_structure;
    126.  
    127. )
    128.  
     
    Last edited by a moderator: Mar 5, 2012
  2. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    Sounds like you have in input/output assigned to either an input only or output only pin.
     
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