error in verilog code....

Discussion in 'Programmer's Corner' started by priyanka24, Dec 31, 2011.

  1. priyanka24

    Thread Starter New Member

    Dec 31, 2011
    suppose i have a binary number i= 00110001
    then i want to count the different run lengths present in this number and send it to output.
    so i get three run lengths for given number as 2,0,3.
    then for this i have written code which is as follows:

    Code ( (Unknown Language)):
    2. module runcount(i, o);
    3.     input [7:0] i;
    4.     output [3:0]o;
    5.      reg [3:0]o;
    6.      integer count=0;
    7.      integer j;
    10.      always@(i)
    11.      begin
    12.      for(j=7;j<=0;j=j-1)
    13.      begin
    15.      if(i[j]==0)
    16.      begin
    17.      count=count+1;
    18.      end
    19.      else
    20.      begin
    21.      o=count;
    23.     count=0;
    24.      end
    25.      end   
    26. end
    27. endmodule

    but in this code me getting syntax correct but as i tried to check its simulation using test bench waveform i get output o as always 'XXXX'.
    so plz help me to find out the error..
    Last edited by a moderator: Dec 31, 2011
  2. bertus


    Apr 5, 2008

    I found this post in the "completed projects" forum.
    As the name told you, it is for completed projects.
    Over there the post will stay invisible, until the mods approve or move it.

  3. PaulEE


    Dec 23, 2011
    Without knowing much about "run lengths", or the code, it appears as though you have a looping structure that is supposed to "look at" the current value loaded into "i", but your "always@" loop refers to "i" also. Did you mean always@(posedge clk) or something along those lines? As is, the code will only execute (I think) when "i" changes.

    I think this is going to be a learning experience for both of us; I do not know verilog all that well...just very basic stuff.
  4. guitarguy12387

    Active Member

    Apr 10, 2008
    Your problem is that you are approaching this as a software problem rather than a hardware circuit. You generally want to have a circuit in mind before you write any verilog or VHDL.

    You need to totally re-think how to do this. But I don't know what you mean by 'run lengths' either. Your code looks like you're just trying to count the number of zeros in a byte (if it were software, that is...). Off the top of my head, a shift register, a 3-bit accumulator, an and gate, and an inverter will get you there with minimal logic and will cost you 8 clock cycles. You could also do it purely combinationally, but will cost you area.

    Point is, design your circuit first. Then think about how to code up each individual building block. Then put it all together.

    For the record, loops get unrolled by the synthesizer. And integers default to 32 bits.
  5. ftsolutions

    Active Member

    Nov 21, 2009
    I agree with both replies above, plus it appears that you may have a logic error in your "for" statement as shown.