Hi,

I'm trying to make a low power emitter follower (so that output matches input) that can be powered by a larger voltage than the supported Vce (see the attached images for the circuit) while still having a fast response time.

The transistor is actually a phototransistor. Initially I tried connecting a resistor between Vcc and the collector followed by a zener (~5.2v) between collector to ground. This ensures that Vce doesn't exceed 5.2v. Then there's a load resistor between emitter and ground. The output is measured at the emitter. In order to get a good frequency response I tried using as small a load resistor as possible.

The problem with this circuit, is if the resistor is too small (such as in the image), the load resistor will form a resistive divider with the collector resistor so that in this instance (Rc= 100k, Re= 30k) it takes a Vcc of 24v for the output to reach the required 5.2v (see graph simulated with pspice).

My second thought was to replace the load resistor with a similar zener which seems to resolve the above issue (see graph).

My question is if this is a good idea and what are the potential pitfalls that I might not know about. What would the frequency response be like for this circuit? I don't have zeners on hand to test this circuit.

Thanks in advance,
M

EDIT: I think the load zener should have a rated zener voltage that is less than the zener voltage of the other zener by at least Vce-sat.

 

This is a prime case of "you need to tell us what you are really trying to do".

 

I'm trying to use this stage to drive a power mosfet gate. The mosfet switches a (relatively) high current load. The stage described above is simply to photoisolate the input from this load.

That's why I don't care if the gate voltage (i.e. output from the previous stage) changes a little around the target gate voltage because the mosfet tolerates these variations. Also, the mosfet won't load the previous stage because the gate has infinite input impedance.

 

What is the maximum switching rate, and the minimum pulse width?
Power MOSFETs have a LOT of gate capacitance, and therefore need drivers with high current capability if the switching speed is substantial. Otherwise, the MOSFET spends a lot of time in the linear region, where it dissipates a lot of power.

 

I don't have a minimum required output pulse width (why would that be important when switching a load?). But minimum switching rate should be at least 1kHz. I'd say 100kHz is more than enough. The input is from a cmos so its pulse width is in the order of ns. The mosfet I'm switching is FDD86252 (http://www.fairchildsemi.com/ds/FD/FDD86252.pdf).

When testing a optoisolator I have here, I found that the maximum switching rate with a 6.2k load was 1kHz. Wouldn't a zener that is conducting act a bit like a current source so it would have a faster switching rate than a resistive load?

Thanks,
M

 

I don't have a minimum required output pulse width (why would that be important when switching a load?).

The rise and fall times have to be significantly less than the minimum pulse width. Faster riseand fall times require higher current transients to charge and discharge the gate capacitance.

But minimum switching rate should be at least 1kHz. I'd say 100kHz is more than enough. The input is from a cmos so its pulse width is in the order of ns. The mosfet I'm switching is FDD86252 (http://www.fairchildsemi.com/ds/FD/FDD86252.pdf).

Do you mean CMOS rise and fall times are on the order of ns? Pulse widths are independent of technology.

When testing a optoisolator I have here, I found that the maximum switching rate with a 6.2k load was 1kHz. Wouldn't a zener that is conducting act a bit like a current source so it would have a faster switching rate than a resistive load?

Thanks,
M

Optoisolators are typically slow. Zeners act as voltage sources, not current sources, and I don't see how you can use them to speed up your switching.
What is the load and voltage that you are switching?

 

Faster riseand fall times require higher current transients to charge and discharge the gate capacitance.

That makes sense.

Do you mean CMOS rise and fall times are on the order of ns? Pulse widths are independent of technology.

I didn't know that. I just went by the data sheets of my output device which happens to be cmos. Why wouldn't pulse width change with technology? Shouldn't a mosfet have a different frequency response than say a bjt?

Zeners act as voltage sources, not current sources, and I don't see how you can use them to speed up your switching.

Sorry, that's what I meant. Because it's a voltage source, the voltage would be the same no matter how much current is pulled by the gate.

The reason why I was asking is that I didn't know how to think of the frequency response of a zener load. I know with a resistor as load, the higher the resistance the slower the response, but a voltage source should have a zero resistance so I was hoping it would have a better frequency response. Somehow I couldn't get pspice to model this (it wouldn't converge if the two zeners have different rated voltages which seems to be required for the load zener to act as a voltage source).

What is the load and voltage that you are switching?

At a minimum it should tolerate a couple of amps with a load voltage of 100v. I couldn't find any (cheap) optocouplers that could switch such high currents (and voltage) so I went with the mosfet.

Since I have you here, I couldn't find any pnp-output phototransistors, do you know why?

The main thing I was trying to do was to power the phototransister output from the (DC) load voltage, which is why I needed the zener to ensure the phototransistor collector is in the safe region.

Thanks,
M

 

Minimum pulse widths are different for different logic families, but this is mainly due to differing transition times. Pulses with fast rise and fall times can be shorter than those with slow rise and fall times. Transition times are pretty much constant across all components in a particular logic family.
It's true that a zener is low impedance when it is conducting, but you can't get any more current out of it than you are putting into it through the bias resistor. If you try, the voltage will drop below the knee, causing the zener impedance to be essentially infinite.
I have never seen a PNP optoisolator. You can run the NPN opto as a high side or low side switch.
I have a circuit you might like to try. I gotta go to bed now, though. I'll post it in the morning.

 

Vishay makes a product that may do what you want. I discovered this after I did the attached design. Kinda gives new meaning to the term "reverse engineering". I would try the Vishay part before proceeding with my discrete driver.
Attached is the design I promised. I've included two versions - one with a push-pull emitter follower and one without. The one with the emitter followers is slightly faster, as you can see.
There is significant shoot-through current in the opto transistors, but their power dissipations are pretty low. At lower frequencies, the duty cycle of this shoot-through is minimal.
If you don't want to run at 100kHz, Dionics makes opto-isolated drivers that are pretty slow.
I have included the .asc file of the LTspice simulation.

 

Thanks, I ordered the components so I can try them out. I'll post if I have more questions.

M

 

It seems that the gate drivers I found all require larger Vcc (e.g. 12v for the Vishay part) than I want to require - about 6v, so it stayed low when I tested it at 6v. I'm imagining they are biased that way because they figure gate drivers typically use larger voltages. The same is with push pull drivers I found which also seem perfect for this. I would rather not have to manually build the circuit you drew.

I did find other non-inverting fast logic optoisolators (e.g. SFH6720T), however, I'm imagining that the problem with those is that they might not have enough current to drive the gate capacitance? Do I calculate the required gate current by rise_fall_time/gate_charge? If so the FQB34P10TM_F085 has a gate charge of 85nC/10ns fall time = 8.5A? While the Vishay part you mentioned has 85nC/100ns = 850mA. Should I really expect such large current spikes?

Anyway, I'm starting to think that I should simply use the optoisolator for isolation (which also inverts the input) and follow it by an inverting gate driver. However, most gate drivers seem to have rise times in the order of tens of ns which seem to translate to very large current spikes, so I'm not sure if I got that calculation right.

Thanks for the help,
M