edge triggered ff with clear

Discussion in 'General Electronics Chat' started by Faizan Ahmad, Apr 19, 2016.

  1. Faizan Ahmad

    Thread Starter New Member

    Mar 6, 2016
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    upload_2016-4-19_21-37-42.png

    What signal should I give to the clr ?
     
  2. Faizan Ahmad

    Thread Starter New Member

    Mar 6, 2016
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    0
    CLK PULSE(0 5 0 0.5n 0.5n 1u 2u)
    D PULSE(0 5 1.6u 0.2n 0.2n 2u 4u)
     
  3. WBahn

    Moderator

    Mar 31, 2012
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    Well, is your clear active-HI or active-LO? It is your design, after all. Isn't it?

    You will want to assert the clear at the beginning of your simulation otherwise your sim might not converge. That or put initial conditions on the charge storage nodes.

    You should also take your ideal signal sources and pass them through buffers so that you get realistic rise/fall times and current drive capabilities. If you don't, this can cause simulation problems if the rapid charge injection causes excessive voltage spikes.
     
  4. WBahn

    Moderator

    Mar 31, 2012
    17,715
    4,788
    Also, I haven't analyzed your design, but it still looks like a master-slave arrangement that will NOT lead to the behavior that you described you were looking for previously, namely that the output changes on the same edge that captures the input.

    Have you looked at the Wikipedia article on flip flops?
     
  5. Faizan Ahmad

    Thread Starter New Member

    Mar 6, 2016
    9
    0
    clear is ACTIVE HI
    this is the o/p if i use nand as inverter



    upload_2016-4-20_9-17-32.png
     
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