Drawing a timing signal diagram for 5 different instructions in an ATtiny2313A (ROM)

Discussion in 'Homework Help' started by meliduong13, Apr 20, 2016.

  1. meliduong13

    Thread Starter New Member

    Apr 20, 2016
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    Hello everyone, just a warning that this message is very long, and I hope it is clear enough, I am trying to put as much useful information as I can.

    I am required to draw a timing signal diagram for a set of 5 instructions (described at the very bottom fo this post) that are programmed in an ATtiny2313A . I do not know how to do so, and would appreciate any help or guidance. I am lost as to what should my timing signal diagram should contain. I know it should contain a certain clock pulse, but which one, from the 555 timer directly? Or from one of the shift register output? (my report is due friday). What else should it contain? How should i draw it?

    Information:
    Two registers (register A and B) receive data from those instructions from the ATtiny2313A and the registers are 74ls173 chips each. They also take different combination of clock signal to output or input values to a bus which all devices are connected to. (will be explained below)

    I have a drawing of my circuit, which does not have all the device completely connected. Because it was a previously done lab. I am still working on updating the diagram. (view file regAregB).
    regAregB.png
    regAregB

    Also the clock is no directly added to the circuit. It has been done separately in another lab report. (view file timer555) Also the 555 is used for the timing signal generation, and connected to a shift register so that it can have its timing divided by 8 pulses. T0 would represent the first pulse connected to led 1, T1 represents the second pulse connected to led 2, and so on.
    timer555.png
    timer555

    The timing signal diagram should be drawn according to an updated version of the circuit (which I dont have, I apologize, still updating it). Therefore. it should have Register A and Register B connected with their input/output enable as follow:

    Output Enable for Register A: OEA = (T4 + Isig0) _ (T4 + Isig2)
    Clock for Register A: CLKA = (T7 + Isig0) _ (T5 + Isig3)
    Output Enable for Register B: OEB = (T4 + Isig1) _ (T4 + Isig3)
    Clock for Register B: CLKB = (T7 + Isig1) _ (T5 + Isig2)
    Output Enable for Sum Register: OESUM = (T6 + Isig0) _ (T6 + Isig1)
    Clock for Sum Register: CLKSUM = (T5 + Isig0) _ (T5 + Isig1)

    Note: Isig is the value outputted to the leds at the rightmost bottom of the circuit design. Where Isig0 would be the value at led0 , and Isig1 would be the value at led 1, so on and so forth.

    The instructions are the following:

    Inc B (instruction 1)

    1. Data Register B outputs its contents onto the bus
    2. SUM Register writes the incremented value of B = B + 1
    3. SUM Register outputs value of B = B + 1 onto the bus
    4. Data Register B writes the contents of the bus

    Inc A (instruction 0)

    1. Data Register B outputs its contents onto the bus
    2. SUM Register writes the incremented value of B = B + 1
    3. SUM Register outputs value of B = B + 1 onto the bus
    4. Data Register B writes the contents of the bus

    MovAB (instruction 2)

    1. Data Register A outputs its contents onto the bus
    2. Data Register B writes the contents of the bus

    MovBA (instruction 3)

    1. Data Register B outputting its contents onto the bus
    2. Data Register A writing the contents of the bus

    NOP (instruction 4)

    NOP is short for no operation. This
    instruction is simply a delay.

    If you have read until this point, I thank you so much!!
     
    Last edited: Apr 20, 2016
  2. DickCappels

    Moderator

    Aug 21, 2008
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    Let's start with the first instruction. Once you do that you should be able to do the rest with little difficulty.

    Inc B (instruction 1)

    1. Data Register B outputs its contents onto the bus
    2. SUM Register writes the incremented value of B = B + 1
    3. SUM Register outputs value of B = B + 1 onto the bus
    4. Data Register B writes the contents of the bus​

    What signals have to be applied to Register B to put its data onto the bus (step1)?
    What signals are necessary for steps 2 through 4?
     
  3. meliduong13

    Thread Starter New Member

    Apr 20, 2016
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    I meant have 1 timing signal diagram for each instruction**
    so for step 1, Output Enable for Register B: OEB = (T4 + Isig1) _ (T4 + Isig3) <- this would be the signal to output to the bus?

    would i have to show all those signals in the timing signal diagram? How would i do that?

    do i still need to draw a clock signal at the top of the diagram? would i draw 8 clock pulses?
     
  4. DickCappels

    Moderator

    Aug 21, 2008
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    It is difficult to even guess given that your schematic is not complete. For example what/where is T4? Where is Isig1? I do not see any place where the contents of B register can be incremented.

    The clocks on your 74LS173s are held at ground by those inverters and your NE555 circuit looks like a random numbers generator.

    Also, all of the LEDs except those in the NE555 circuit appear to be backwards, so please double-check.

    Maybe it is because I lack imagination or maybe I am just not familiar with your notation, but I cannot see how the circuit can work as you want.
     
  5. meliduong13

    Thread Starter New Member

    Apr 20, 2016
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    the 555 outputs a consistent pulse that is divided into 8 different pulses labelled from t0 to t7.
    I have tried to relabel this more clearly:
    so t0 is indicated by the arrow on the LHS, and t7 is indicated by the arrow on the RHS. in between is t1 to t6.
    Therefore you can see where t4 is.

    Also I know my diagram is incomplete. I will add the inputs required
     
  6. meliduong13

    Thread Starter New Member

    Apr 20, 2016
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    DIscard the previous message, i posted it by mistake. I have added clarifications below, hopefully it my question make more sense.

    the 555 outputs a consistent pulse that is divided into 8 different pulses through a shift register. the pulses are labelled from t0 to t7.
    I have tried to relabel this more clearly:
    so t0 is indicated by the arrow on the LHS, and t7 is indicated by the arrow on the RHS. in between is t1 to t6.
    View attachment 104763

    I have label Isig0 to Isig2 below (look at the bottom right corner, its small), but did not have enough space to label the rest. Also the registers should be rewired following the equations that are put right next to them. for register A and B, the pins 1 and 2 should be rewired to the equation displayed next to them. and each of the pin 7, should be rewired like the equation below them (CLKA and CLKB). See below
    regAregB.png


    The sum register comes from here:
    the sum register has been re-wired following the equations . the clock register equation has been used to rewire the pin 10 and the output enable has been used to rewire pin 9.
    t0 represents pc-out
    t1 represent sum-in
    t2 represents sum-out
    t3 represents pc-in.
    View attachment 104764
     
  7. meliduong13

    Thread Starter New Member

    Apr 20, 2016
    5
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