doubts regarding clock frequency of 18f4550

Discussion in 'The Projects Forum' started by embpic, Apr 2, 2014.

  1. embpic

    Thread Starter Member

    May 29, 2013
    187
    3
    i have doubt regarding oscillator frequency.
    i am using 18f4550, XC8 compiler, primary oscillator of 20MHz. i have kept following configuration

    Code ( (Unknown Language)):
    1. // CONFIG1L
    2. #pragma config PLLDIV = 5       // PLL Prescaler Selection bits (Divide by 5 (20 MHz oscillator input))
    3. #pragma config CPUDIV = OSC1_PLL2// System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
    4. #pragma config USBDIV = 2       // USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes from the 96 MHz PLL divided by 2)
    5.  
    6. // CONFIG1H
    7. #pragma config FOSC = HSPLL_HS  // Oscillator Selection bits (HS oscillator, PLL enabled (HSPLL))
    8. #pragma config FCMEN = ON       // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor enabled)
    9. #pragma config IESO = ON        // Internal/External Oscillator Switchover bit (Oscillator Switchover mode enabled)
    10.  
    11. // CONFIG2L
    12. #pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)
    13. #pragma config BOR = SOFT       // Brown-out Reset Enable bits (Brown-out Reset enabled and controlled by software (SBOREN is enabled))
    14. #pragma config BORV = 2         // Brown-out Reset Voltage bits ()
    15. #pragma config VREGEN = ON      // USB Voltage Regulator Enable bit (USB voltage regulator enabled)
    16.  
    17. // CONFIG2H
    18. #pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
    19. #pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)
    20.  
    21. // CONFIG3H
    22. #pragma config CCP2MX = ON      // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
    23. #pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
    24. #pragma config LPT1OSC = OFF    // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
    25. #pragma config MCLRE = ON       // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
    26.  
    27. // CONFIG4L
    28. #pragma config DEBUG = 1
    29. #pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
    30. #pragma config LVP = OFF        // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
    31. #pragma config ICPRT = OFF      // Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
    32. #pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
    33.  
    so i am using oscillator mode as HSPLL for USB, and PLLDIV is 5 for derive 4MHZ frequency for PLL input for deriving 48 MHz clock.

    I have confusion in system clock.
    is following bits decide of system clock??
    11 = 96 MHz PLL divided by 6 to derive system clock
    10 = 96 MHz PLL divided by 4 to derive system clock
    01 = 96 MHz PLL divided by 3 to derive system clock
    00 = 96 MHz PLL divided by 2 to derive system clock

    if yes then what is time for Machine cycle?

    how to check frequency on which pic is running using pickit3 ??
     
  2. THE_RB

    AAC Fanatic!

    Feb 11, 2008
    5,435
    1,305
    A good method to find out what clock frequency the PIC is running at is to set TMR0 to 1:1 prescaler, and use this very simple code;
    Code ( (Unknown Language)):
    1.  
    2. TRISB = 0x00;  // portb is outputs
    3. while(1)
    4. {
    5.   if(TMR0L >= 128)  LATB = 0xFF;
    6.   else              LATB = 0x00;
    7. }
    8.  
    What that does is to output a frequency on the PORTB pins where the frequency is the instruction speed /256.

    So if your clock speed is 48 MHz, inst speed is 12 MHz, and the freq output is 12MHz/256 = 46875 Hz.
     
  3. ericgibbs

    AAC Fanatic!

    Jan 29, 2010
    2,503
    380
    Look at this marked up clip from the datasheet.

    The Basic CPU clock [refer image] is further divided internally to produce 4 machine timing periods.

    So a 20MHz Xtal divided by 2 would give give a CPU clock of 10Mhz, this is always divided internally by 4, so an Instruction cycle would be 400nSec

    To double check, use Roman's method.

    E
     
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