double gate mosfet project

Discussion in 'The Projects Forum' started by siddhiq, Oct 31, 2013.

  1. siddhiq

    Thread Starter New Member

    Oct 31, 2013
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    Hi,

    Iam doing my final year project on double gate mosfet using finfet 32nm....I have simulated the full adder using cmos logic styles such as pass transistor logic, conventional logic etc......

    My results for power and delay are better for conventional than pass transistor logics which is expected to perform better....am using the 28 transistor model for conventional logic...simulation is done using hspice.....

    Also varying the load capacitance varies the power-delay characteristics and at at CL=10pf ,cpl(complementary pass transistor logic) is said to be performing better than conventional and it varies for different CL.....Can any please help me?.....what is the optimum value for CL?....

    Thanks in advance...
     
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