Double buffered data latch - parallel input

Discussion in 'Embedded Systems and Microcontrollers' started by atferrari, Dec 30, 2013.

  1. atferrari

    Thread Starter AAC Fanatic!

    Jan 6, 2004
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    In my design, every so many usec I output row/columns data (5 bytes x 8 bits ea) all at once. Up to now, I could go away with the 74HC595 serial shift register but since I need it to be faster, the time it takes to shift the 40 bits in and then show them all at once is more than what is available for each "frame".

    Thinking of doing something similar with parallel input data latches strobing the 5-bytes output at once, I could not find an IC able to keep the previous value at the output UNTIL the 5 new ones are sequentially loaded.

    Checked the 74HC373,374,573,574 variations but they all lack an intermediate register that would allow the succesive input of bytes while the previous data is still shown.

    Any chip that I could have overlooked and is easily available? Even browsing the long list in the data books in paper in my library I couldn't find one.
     
  2. MrChips

    Moderator

    Oct 2, 2009
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    How about using a pair of 74HC574?
     
  3. MrChips

    Moderator

    Oct 2, 2009
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    Have you looked at CD4034?
     
  4. atferrari

    Thread Starter AAC Fanatic!

    Jan 6, 2004
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    Have read and reread the datasheet but not sure it can hold the data until I strobe all bytes at once.

    Anyway, locally, it is crazily expensive (about 7 USD/ea).:eek:

    Thanks for replying.
     
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