Does latch require setup time before rising edge?

Discussion in 'General Electronics Chat' started by dMoser, Jan 24, 2012.

  1. dMoser

    Thread Starter Member

    Aug 25, 2011
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    I learned that setup time for latches is the time before clock's falling edge in which data needs to remain stable.

    Say that just as clock's rising edge arrives, data become stable, will Q become valid after Tpdq?

    Thanks.
     
  2. Brownout

    Well-Known Member

    Jan 10, 2012
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    That depends on if the latch captures data on the rising or falling clock edge.
     
  3. dMoser

    Thread Starter Member

    Aug 25, 2011
    30
    1
    This is a transparent latch, meaning it passes data when clock is up.
     
  4. Brownout

    Well-Known Member

    Jan 10, 2012
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    998
    In that case, I'd say yes. Best to verify with the datasheet though.
     
  5. MrChips

    Moderator

    Oct 2, 2009
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    You need to specify the part number.
    If it is a transparent latch that latches the data on the falling edge, e.g. SN7475, no setup time on the rising edge is required. Setup time for SN7475 is 20ns prior to falling edge.
     
  6. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    On second thought, there might be a different time specification from clock to Q-Data. That's why you need to verifiy with the datasheet.
     
  7. dMoser

    Thread Starter Member

    Aug 25, 2011
    30
    1
    Thank you guys!
     
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