I have to change this circuit so it will work with all NAND gates. My first step is labeling all the gates. Can somebody tell me if I have labeled all these right.
Thanks
Thanks
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Can I point out in (b), the lower AND gate with inputs DBD' is a superfluous gate since DD' will always equal 0. In other words no matter what input combination DBD' is the output will always be 0.I have to change this circuit so it will work with all NAND gates. My first step is labeling all the gates. Can somebody tell me if I have labeled all these right.
Thanks
by Duane Benson
by Duane Benson