Hello everyone,

I'm having a bit of trouble with figuring out a way to divide two sinewaves. I'm going to have two sinewaves, which are out of phase by an unknown amount. The phase-change isn't constant.

I want to be able to get a constant value from each waveform, which is the ratio of the two sinewaves. I was thinking of using an averaging scheme, then divide the RMS values of both waveforms. I need the system to act as quickly as possible, so I thought this would be a laggy method. This is all being done in the digital domain. I was thinking of sampling 5 periods, then averaging, then dividing. It is for a control system, so I want the fastest response possible.

The idea is to have a carrier voltage at ~5KHz and recieve a current from an unknown inductance. The ratio of voltage to current yields this inductance. This technique of measuring inductance is needed in my application, I understand that there are other methods.

Any ideas?

Steve

 

the fastest way i think would be by implementing a microcontroller. what do you think?
detect the period of each signals, then detect every peaks in a period, and calculate the division.

 

How do you plan to divide by zero? Sinewaves still have zero crossings -- don't they? You could also use log amps, subtract, and take the anti-log.

 

sinx = cos (x-pi/4)

tany = sinz/cos(x-pi/4)

 

rwmoekoe,

I'm using an FPGA for this, sorry I didn't mention it before. I have the ability to place a microcontroller on the FPGA and run C-code, but I would rather a hardware solution.

Papabravo,

Yes, the zero division is definitely something that I am concerned about. I have accepted that it would be too difficult to lock the waves together and do a free-running division, I need some sort of scheme to do this properly. I know the frequency of the waveform, so I am thinking of using zero-crossing, then time exactly the time it takes to get to the peak, then store that value. Two registers will constantly store values and be input to an asynchronous divider.

studiot,

I'm confused by your post and how it could help with my issue...

Steve

 

Well I'm pretty sure that a uP core running C code is going to be a bit slower than doing a division in hardware. The most straight forward hardware divider is one that will depend on the number of bits in the divisor.

Try this link:
http://courses.cs.vt.edu/~cs1104/BuildingBlocks/divide.030.html

 

The ratio you want is the ratio of amplitudes of the two sines (eg updating after measuring the amplitude), or momentary (eg changing all the time)?

If it is the first, then if the signals are strictly sinewaves, you could measure peak-to-peak voltages, and after a min and max of any of the two signals has been updated recount the ratio.

I think this could be done even with standard logics and a few D-latches and buffers, if you have the digital samples in parallel mode.

 

how about a standalone 8 lead pic with internal rc oscilator, 2 adc inputs to do the work, serial output to your registers to get the work done neatly, precisely and compactly.
instead of lots of discreet components... you know...

 

I off course meant using some high-level programable logic array, like FPGA and similar.
But I think that for more than 8 bits the FPGA would coast a lot more than some suitable uProcessor.
But on the other side I thing that "discrete" design with FPGA can be suitable for high frequencies and when you need really fast response like after each cycle of the sines.

 

Papabravo,

Thanks for response, I am thinking of using a hardware divider, but the problem is really the inputs to the divider itself. I am interested in the difference in amplitude of the two waveforms, which are unfortunately out of phase and on two separate and changing bias voltages.

kubeek,

Thanks for the advice. I do not need cycle to cycle precision, but I would like to have something close to that. I cannot accept anything that would take longer than 10 periods to figure out a ratio though. I like your min and max idea, it seems implementable. I'm going to browse around to see if I can find any routines that find min and max within an FPGA architecture.

rwmoekoe,

This is a sub-system of a larger design, which is using two 2M gate FPGA devices. The raw power of this device running parallel processes would out-do any 8-bit processor. I can implement a 32-bit processor on-board, but I want to shy away from that sort of thing for now.

Steve

 

Is not the ratio of two sine (cosine) waves equal to the tangent?

This also avoids the question of division by zero.

The only thing left is to arrange a proper phase realtionship to all refer to the same origin.

 

For the min and max circuits, you just need to find a comparator, which should output 1 if the word1 is higher than word2. then load that word into register.

The division can be implemented by 256x256 table of values (assuming 8bit percision), and you can even have the output in different number of bits so you can have for example 24bit precision on the output.

What is your signal precision and target frequency of the signals?

 

studiot,

Sorry, I understand what you're saying, but I cannot see how that can be practically implemented. First of all, my phase is unpredictable, so I cannot assume a pi/4 shift and divide. I have two completely distinct signals with the exception of frequency, which need to be compared.

kubeek,

Thanks again for the help. I am working with about 10 bits of precision and the sinewave should be less than 5KHz. You've made me realize that I cannot easily divide with the FPGA, I thought it would be an easy task I don't think I can spare 1Mbit of data for a lookup table either. I wanted to shy away from using external memory, due to timing and interface complexity.

I need to draw up a scheme that will work, perhaps I should just implement a microcontroller on the FPGA itself for operations such as this. I didn't want to go that route due to having to learn wishbone interfaces and such.

Steve

 

Do you have the whole FPGA just for this? If it can be programmed in HDL or some similar language like Xilix´s chips are, then the programming software should optimise the table so it can be much smaller than 1meg.
Or you can try to find some example of divisor.

 

kubeek,

The FPGA does a lot of other things, including PID, PWM, serial-parallel from ADC, polynomial fits, X four channels. I'm using the DSP Toolbox for Xilinx to do this, I'm not sure if it does code compression, but i'd hope it would if it is possible.

Steve

 

I'm probably barking up a tree here, but couldn't one simply feed the waves into a difference amp and digitize the o/p?

 

hey thingmaker,

A difference amplifier can be used, you're right. I can put a 2nd order filter which is in the order of what I would like as a response, then digitize the output. But, the catch is, I am doing a lot more with the information that I am currently digitizing. It is being used for three different tasks, through different filters.

Steve

 

But a diff amp won't give you the scalar ratio of the amplitudes of the two signals. It will give you the vector difference.

 

Ron, you're right! My mistake
I was trying to keep on the line of thought, "You're just trying to find the difference between the input signals to give some information", but that notion is faulty. The ratio is key, which is the inductance in my case!

Steve

 

kubeek,

The FPGA does a lot of other things, including PID, PWM, serial-parallel from ADC, polynomial fits, X four channels. I'm using the DSP Toolbox for Xilinx to do this, I'm not sure if it does code compression, but i'd hope it would if it is possible.

Steve

I had a class in logics this semester, and we used ModelSim with some xilinx board to do the usual simple logic things like adder and such.
They also showed us that you can define a function of a black box by table, like that you enter some set of output values for different inputs, and the program then optimizes it for the chip.
But I don´t know how usable is that for a million entries, maybe making some script to count the divisions and create the VHDL file could do it.
But there is still the question if the resilult can be fitted into the chip.


But there surely is a way to compute it. You shouldn´t need a processor for that, because you know the maximal length of the numbers, so you don´t need a loop which goes through all the bits like in standard division procedure.

You can first remember how you do division of large numbers by hand on paper. Then try it with binary numbers, then you should be able to implement it with a series of logic steps for know word length.