divider ip core problem!

Discussion in 'Embedded Systems and Microcontrollers' started by charko, May 27, 2010.

  1. charko

    Thread Starter New Member

    Apr 27, 2010
    Hi everybody!
    I want to implement in vhdl a divider. So i want to use an ip core if i want to have a fast divider.
    The divider can used for the calcul of interpolator. The algorithm for interpolator linear is : f= ya + lamda x ( yb -ya) and lamda= (x-xa)/(x-xb).
    When i write a code vhdl ( vhdl structural) for adder, multiplier and substractor i compile it and i simulate it and evrything is ok.
    So When i implement an ip core divider and simulate it i have at divider output
    You can show in the attachement , the picture for the architecture, picture divider simulation and picture of the interpolation simulation.

    I hope that i clarify my problem.
    I will be grateful for your help.
    Thank you.

    PS: Sorry for my bad english.