Divided by N counter of the PLL

Discussion in 'General Electronics Chat' started by dumindu89, May 19, 2012.

  1. dumindu89

    Thread Starter Member

    Oct 28, 2010
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    I need t know few things about the divided by N counter of the Phase Locked Loop (PLL).

    What is the output of the divided by N counter of the PLL? Is it the bit pulse of count or what?

    As an example let's say Input frequency is 22 MHz, and the N = 500. Then what type of output should be come at the N counter? (I am talikng about the output at divided by N counter, not at the VCO)

    [​IMG]

    Please help me. This is an urgent.
     
  2. bertus

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  3. t_n_k

    AAC Fanatic!

    Mar 6, 2009
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    Presumably the divide-by-N counter output goes to the phase comparator. So the divide-by-N counter output frequency will match the the other phase comparator input. If that's 22MHz then the divide-by-N counter output frequency will also be 22MHz.
     
  4. dumindu89

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    Oct 28, 2010
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    Great. I got the idea. But I have few more things to know. :)

    If the desired output frequency at the VCO F = 88 MHz, and reference frequency is Fr = 0.1 MHz. If I am using a prescaler as shown in the following diagram for the PLL.

    [​IMG]

    We know that F = N*Fr and then N = F/Fr. If I need to get the count for this configuration how should I use this equation?

    I mean is it N = 88MHz/0.1MHz or N = 22MHz/0.1 MHz ??
     
  5. crutschow

    Expert

    Mar 14, 2008
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    It would be the latter, N = 22MHz/0.1MHz or N = 220. The idea is that the two signals into the phase comparator have the same frequency when the loop is in lock.
     
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  6. dumindu89

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    Oct 28, 2010
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    Thank you very much for the quick reply. :) Got that.

    But I realized another issue. :(

    I need to design a Programmable divided by N counter for a FM transmitter using counter ICs available in the current market. (I am not talking about CPLDs or programmable dividers available in PLL chips) It should be able to programmable (change the count from parallel load inputs) one to change the output frequency at VCO (88MHz to 108 MHz with 100 kHz steps) by changing the count; N.

    According the calculations then the count range will be 220 to 270 (with such a prescaler). There are just 50 channels. But 88MHz to 108 MHz with 100 kHz steps means there should be 200 channels.

    How I achieve 200 channels with such a prescaler (count increment is 1) ?
     
  7. bertus

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    Apr 5, 2008
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    Hello,

    With the prescaler you have now you will have steps of 4 X Fr = 4 X 100 kHz = 400 kHz.
    What needs to be changed to have 100 kHz steps you want?

    Bertus
     
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  8. dumindu89

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    Oct 28, 2010
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    Ahh.. Change the reference frequency to 25 kHz. Thnx. :)

    I need to know few methods to design a programmable divided by N counter using counter ICs as I stated in the earlier post. Count range will be 880 to 1080.
    Please let me know about it too.
     
    Last edited: May 19, 2012
  9. bertus

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  10. dumindu89

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