# Divide the frequency using a down counter

Discussion in 'General Electronics Chat' started by dumindu89, Jun 6, 2012.

1. ### dumindu89 Thread Starter Member

Oct 28, 2010
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I need to divide the input frequency (let's say divide by 50) using the down count mode of the 74192 UP/DOWN decade counter. I will use the parallel inputs to give the desired count value. Since the count is more than 10, I will need cascade counters.

Datasheet of 74192 IC: http://pdf1.alldatasheet.com/datasheet-pdf/view/23048/STMICROELECTRONICS/74192.html

2. ### MrChips Moderator

Oct 2, 2009
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3,362
Do you a fixed divide or is the number selectable?

For a fixed divide by 50, you need two counters. Divide by 5 followed divide by 10.

The counter does not have to be UP/DOWN counter. You can use any UP counter.

3. ### dumindu89 Thread Starter Member

Oct 28, 2010
113
0
Nope. It is not a fixed divide. The number is selectable. Can I do it using down count mode? How should I configure the pins to do this frequency divide?

4. ### MrChips Moderator

Oct 2, 2009
12,447
3,362
Next questions:

1) What is your input clock frequency?
2) What is the range of frequencies you need?
3) At what resolution?
4) From the above, you can answer what are the numbers you need in your divisor?
5) What are you trying to build?

There are such things as binary rate multiplier, phase looked loop oscillator, digital frequency generator/synthesizer.

5. ### dumindu89 Thread Starter Member

Oct 28, 2010
113
0
5) Programmable divided by N counter for a PLL
2) It varies from 88MHz to 108MHz. You know that, F = NxFR.
Finally, the output frequency of the divider should be the referance frequency,FR. ( FR is 100 kHz). I will set the desired count, to get the output frequency (F) at the VCO.
4) 880 to 1080
3) What do you mean as the resolution?

Oct 2, 2009
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7. ### dumindu89 Thread Starter Member

Oct 28, 2010
113
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Hi!
I just need how to configure the 74F192 IC (I already selected 74F192) to get the frequency division.
For example: Which pin will give the divided frequency as the output from the last 74F192 IC of this cascaded system if I used down count mode? etc.

Oct 28, 2010
113
0

9. ### MrChips Moderator

Oct 2, 2009
12,447
3,362
If you are counting down a 74192 counter the divided frequency output will be BORROW.
To get 50% duty cycle you have to feed this into a T-flip/flop (an additional divide by 2 stage).

10. ### dumindu89 Thread Starter Member

Oct 28, 2010
113
0
Hi
Where should I place the T flip flop?
Why do I need it?
Then how I connect asynchronous parallel load pin of each counter?

11. ### MrChips Moderator

Oct 2, 2009
12,447
3,362
You take the BORROW output from the 74192 and feed this into the CLOCK input of a T-flip/flop which can be created from any D, T, or J-K flip-flop.

You feed the BORROW signal to the LOAD input.
I would have to breadboard this to be sure.

dumindu89 likes this.
12. ### dumindu89 Thread Starter Member

Oct 28, 2010
113
0
Do you mean the configuration like this (without the T flip flop)?

13. ### dumindu89 Thread Starter Member

Oct 28, 2010
113
0
What should be the input for the T input?

14. ### MrChips Moderator

Oct 2, 2009
12,447
3,362
T input should be 1.
Usually, you cannot buy a T-flipflop.
You have to use a D, J-K or divide-by-2 stage.

15. ### absf Senior Member

Dec 29, 2010
1,493
372
I wire up the 74192 and simulated it with a divisor of 60. I setup a 3rd 74192 to display the results. Before connecting the JK FF to divide the result by 2, the 3rd 74192 immediately increments by 1 when power is applied. With the JK FF, the up-counter would first increment after 60 counts and subsequently increments after every 120 counts.

My clock input is 5% duty cycle at 4 Hz.

Any ideas?

Allen

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Last edited: Jun 7, 2012