Divide-by-N counters

Discussion in 'General Electronics Chat' started by bob800, Oct 27, 2012.

  1. bob800

    Thread Starter Member

    Dec 10, 2011
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    Hello,

    I'm trying to build a composite video generator as described in Don Lancaster's TV Typewriter Cookbook.

    I've attached the diagram in question, but ignore the PLL circuitry for now. My questions only concerns the divide-by circuitry:

    1. I'm assuming that each of the arrows coming off the counters symbolize data bits (e.g. 1,2,4,8 for the /64 counter). Am I correct in thinking that the counter will count up by '1' in binary, once every 64 clock pulses?

    2. I'm assuming that the east-facing arrow coming out of the /64 and /264 counter is simply connected the the LSB of the counter output?

    3. Could a /64 counter be built by connecting the MSB from a 4-bit counter to the input of another 4-bit counter, and then connecting the MSB of this counter to a third counter?

    4. How would one build a divide-by-264 counter??


    I apologize in advance for my stupidity :D
     
  2. panic mode

    Senior Member

    Oct 10, 2011
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    yes each arrow coming out of the divider/counter is bit. but remember that each FF or counter stage divides input frequency by 2. therefore LSB is the first one, not the last one. the one that goes to next stage is the MSB which is slowest changing.

    you can cascade counters to obtain different division. so if you want divide by 64 but only have 4-bit counters at disposal, you can daisy chain them. you get 8bit counter which would have 2^8=256 counts. since you need divide by 64, you would simply use bit-6 as output.

    264 is not base2 value so we need to see how it is factored.
    264=2*132
    =2*2*66
    =2*2*2*33

    the 33 can't be factored any further.
    one solution is to use 6-bit counter and reset it when it reaches 33. then add 3-bit counter to divide by 8. you could change order of counters but this way you get output (the last three bits) that is 50% duty cycle.
     
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  3. MrChips

    Moderator

    Oct 2, 2009
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    33 = 3 * 11
     
  4. WBahn

    Moderator

    Mar 31, 2012
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    Agreed. I think panic mode meant that it can't be factored by 2 any further, since he was trying to identify how many bits worth of full-cycle counters could be used. But if you want to stick with just 4-bit counters, for some reason, factoring it further could be helpful.
     
  5. bob800

    Thread Starter Member

    Dec 10, 2011
    48
    3
    This would make sense, but then why are there only 5 arrows (5 bits) coming off the /64 counter? With 5 bits, the MSB would act as a /16 counter... And then why are there only 5 bits coming off the /264 counter??! Are those the 5 least significant bits, or... what am I missing?

    The only "explanation" I could come up with was that the counters increment every 264 clock pulses, so that the LSB would essentially act as the /264 output, with the output bits simply counting up to 31 and then resetting...
     
  6. takao21203

    Distinguished Member

    Apr 28, 2012
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    You could use PICs for that, the baseline models are cheap.
    You only need one type of chip! Simply use the input signal as clock source.

    This is of course still a waste, eventually you can implement circuits like this with much less components, using modern controllers. But I understand you want to recreate these circuits somehow.
     
  7. bob800

    Thread Starter Member

    Dec 10, 2011
    48
    3
    Sure, but my goal is to build a Z80-based computer without any using any high-level components...
     
  8. takao21203

    Distinguished Member

    Apr 28, 2012
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    The 16f5x are quite simple chips, very similar to the original PICs designed in the late 1970s. They don't really have high-level functionality.

    You can however use them for things like complicate counters- you save money, and circuit space, and only need one type of chips.

    For instance for the 1:264 counter, you only need one chip. The 16f54 has 25 bytes RAM, and 512 bytes FLASH, so it is not too much high level. I mean, you won't be having a chip in your circuit that is far more powerful than the z80 already.

    Most of these chips in Don Lancasters books are now obsolete, unavailable, or hard to find + expensive at best. I know his website too, by the way.

    So maybe you will be using GALs? For sure some z80 circuits use them. But they are complicated to use, expensive, and not much supported anymore.

    I understand you want to build a z80 computer. Somewhere there is a line between the external functionality that you want, and the efforts/costs of the old, original hardware.
     
  9. bob800

    Thread Starter Member

    Dec 10, 2011
    48
    3
    Other than the character generator ROM, I've had no trouble finding equivalents of the chips he uses. Sure, in one of his magazines, Lancaster make use of huge 512-bit shift registers instead of (then expensive) static rams. But I think if you read through the linked PDF, most of the parts (RAMs, simple shift registers, and counters) are still readily available and cheap. And aside from the video generator board, all I need for a functional Z80 computer is some ram, eeprom, buffers, and decoders. Practical? No. Readily available? Yes.

    The only reason I'm hesitant to use a PIC for counting is that I'd have to deal with additional timing delays, programming, etc. But I appreciate your suggestion and may consider using PICs for more complex boards (IDE interface, etc.)
     
  10. takao21203

    Distinguished Member

    Apr 28, 2012
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    I have downloaded the PDF yesterday, and skipped through it.
     
  11. bob800

    Thread Starter Member

    Dec 10, 2011
    48
    3
    Could anyone please clear up my confusion in post #5? That's what I really need to know before I continue with the project...
     
  12. panic mode

    Senior Member

    Oct 10, 2011
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    no, that was just generic block diagram not a real circuit. number of arrows is irrelevant here as it represents "outputs" (ie. ANY number of outputs). actual number would depend on number of stages of counter....
     
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  13. JohnInTX

    Moderator

    Jun 26, 2012
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    I actually designed and built a CRT terminal using Don Lancaster's original Radio Electronics article as a guide... in 1975 or so.. sheesh.. Then I bought an ADM-3A .. steppin' in some tall cotton there, I tell you. Anyway, here's what I remember about it..

    I used an earlier (NTSC) version of one of these to generate the horizontal / vertical sync. I fed the dot clock into a chain of synchronous timers (74LS161 See Fig 1 on the datasheet) with feedback to make them count 0-x for each stage of the raster display:
    0-5 for the 6 column (5 char dots plus a blank) dot row on each scan line feeding..
    0-63 for 64 chars per line feeding..
    0-7 for 8 dot rows per char feeding..
    0-24 for 25 chars per line..
    .. to make up one frame of 64x25 chars/screen.

    The divide by N is performed by using the synchronous load (to 0 in this case) function. Ref the first stage, when the count is 5, the AND gate (with inverted bit) will put a 0 on the LOAD/ of itself and 1 on ENT of the next stage. On the next dot clock, the first stage will reset to 0 (start the first column of..) and the next stage will increment (..the next character).

    By doing it so, the intermediate counter values provide appropriate numeric outputs to drive the data RAM, 2513 character generator, and dot serializer (using a 74LS151 8-1 mux.) The sketch shows the basics. Sorry its ratty.. its a quickie but you should get the idea. (I'm surprised I remembered this much). I didn't spend much time with the actual logic (ENABLE sense on the MUX, RAM R/W/OE control etc) so its more of a concept than a schematic..

    Note that the RAM address repeats 0-63 8 times (once for each of the char rows plus a blank) to do one line of 8 row characters then picks up the incremented CHAR LINE COUNT to do characters 64-127 eight times etc..

    Also note is I wrote the RAM. This one handles it by multiplexing the address and driving the data bus for the write and using the enable line on the 151 to blank the dot output during the write cycle to prevent flicker (the phosphor persistence masks the blanking).

    Originally, I drove a TV through a photodiode opto tap to the video section to bypass the tuner. Worked OK. You'll have to combine the horiz, vertical sync with the dot video to do a composite monitor. I eventually used a Ball monitor with H-V-I inputs. Finally, I bought an ADM-3A. And today, I use Procomm with a PCI serial card..

    But if you MUST, here's one way to do it. I know the 2513 is hard to find but you'll get the idea.

    BTW: Going to a full 80 char/line proved problematic as 80 isn't binary so required parallel counter chains.. I think that's when I went to the ADM-3A.

    Whew! Have fun.

    EDIT: ADM-3A manual with schematics!

    And now, having achieved dumb terminal nirvana, its time to pop a top.
     
    Last edited: Oct 28, 2012
    bob800 likes this.
  14. MrChips

    Moderator

    Oct 2, 2009
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    I may still have an MM5321 video sync generator laying around from previous projects.

    I too built a SWTPC CT-1024 Video Terminal and might still have the schematics if anyone is interested.
    (I use the schematics as an example of the worst piece of hardware drawing I have ever seen.)

    Also assembled many ADM3A when they were first sold as kits. Still have the manuals.
    I added a graphics board which overlayed 256x256 graphics with the text screen.

    MCUs are fast enough today that you can do the sync generation entirely on one MCU chip, AND the complete video generation as well. My ARM project has been put on hold for the time being until I can get caught up with usual work related projects.
     
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