This is my first post and I apologize if this is not the right place to post this. Would be much obliged if the moderators can let me know if this needs to be posted elsewhere.

Anyway, one of the questions that I have seen interview candidates struggle with, is the divide-by-3 counter/clock divider. It has been a while since I actually did any sequential circuit design using the state-machine drawings, but nevertheless I decided to give this a shot:

Ok! here goes

1. The waveform goes as 110110110 (or 001001001) with each state transition occurring on the +ve edge of a clock. It is a lot easier to understand if you can draw the waveform
2. Taking the transition at each +ve edge of the clock as a 'boundary' for state change, we have 3 stages - namely '00', '01' and '10'. After '10', the next clock cycle brings you back to '00'.
3. 3 stages means a minimum of 2 Flops - D-FF in my case
4. K-maps will give you the following equations:
D1 = Q0
D0 = Q1 XNOR Q0
Z (output) = Q0\ + Q1
I have assumed a "don't-care" for the '11' state.

I would much appreciate if anybody can confirm that this will work as a "divide-by-3" (though not with 50% duty-cycle) clock-divider. Of course, corrections are most welcome.

 

Hello,

Here is a PDF with a discussion on how to make odd dividers with 50% duty cycle.

Greetings,
Bertus

 

Thanks. I guess the difference stems from the "don't-cares" and whether you want to consider them or not.

 

Hello,

In a table the "don't care" value is either 0 or 1 , but this does not change the result.

Greetings,
Bertus