Discussing Half line discrepancy effect in interlaced scanning....

Discussion in 'General Electronics Chat' started by Himanshoo, Jul 21, 2016.

  1. Himanshoo

    Thread Starter Member

    Apr 3, 2015
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    Hi guys,

    The thing which i am not getting is that with the addition of equalising pulses the capacitor voltage value in both the field reaches to the same zero value at point X. But how exactly is this happening, what I mean to say is that when the capacitor is charging under the influence of equalising pules have small discharge time which causes the capacitor to not discharge to the zero level till the fourth equalising pulse but suddenly after the commencement of the fifth equalising pulse the voltage level drops to zero. Since during the previous four equalising pulse the voltage of capacitor for both the fields is different as shown in figure but after the end of fifth pulse it is same for both the fields..so whats so special happened after the 5th equalising pulse which brought both the voltage values to zero.

    regards!

    Screen Shot 2016-07-21 at 12.20.27 pm.png
     
  2. crutschow

    Expert

    Mar 14, 2008
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    That drawing is perhaps a little misleading.
    The voltage decays at an exponential rate until it reaches a steady-state value based upon the equalizing pulse period, pulse width, and pulse voltage, along with the circuit time-constant (and I think that voltage is not "essentially zero" but is likely some value slightly more than zero).

    The voltage becomes essentially equal for both fields because, in each case, the voltage decays to the point where the voltage equals the exponential decay between each set of pulses, as if there were an infinite number of equalizing pulses.
    In other words if there are enough equalizing pulses, then the voltage becomes the same, independent of the starting voltage.

    For the time-constants and frequencies chosen for analog TV, five equalizing pulse are sufficient to give a voltage essentially equal to an infinite string of pulses for either field's starting voltage.

    Note that, for proper vertical sync operation, it's not necessary that the voltage at the start of the vertical sync pulse be zero, just that it's the same voltage for all frames.

    Make sense?
     
  3. Himanshoo

    Thread Starter Member

    Apr 3, 2015
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    I am not getting these line...

    needs elaboration...
     
  4. Papabravo

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    When the voltage on a capacitor decays, it asymptotically approaches zero. It can never get to zero, but it gets very close. Similarly when a capacitor is charged toward a fixed voltage, it can never actually get there, even after an infinite amount of time. Five pulses gets it close enough so the difference does not matter.
     
  5. Himanshoo

    Thread Starter Member

    Apr 3, 2015
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    Yes I agree...... but as you see in the figure that the capacitor voltage is a little far than zero during the four pulse but as soon as the fifth pulse ends the volatge is move a little near to zero...

    Why this is so??
     
  6. Papabravo

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    After the fifth vertical sync pulse the voltage is just above the trigger level. It is the following pulses with the lower duty cycle where the decay back to zero takes place. If you are talking about the five pulses just before the five vertical sync pulses, their duty cycle is such that the capacitor discharges to near zero before the first of the sync pulses arrives.
     
  7. Himanshoo

    Thread Starter Member

    Apr 3, 2015
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    But according to text the pulse width of equalising pulses is 2.3 μs...so if pulse width of all equalising pulse is constant then how duty cycle could be different for the fifth pulse...
     
  8. Kermit2

    AAC Fanatic!

    Feb 5, 2010
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    You are obsessing over the scaled timing diagram.
    It is not an EXACT diagram of what is happening, but is conveying the CONCEPT of the action over time. The perceived RC time decay discrepancy you have zeroed in on is NOT happening as pictured.
    The pulses give short charging input that overwhelms the timing offset of the two scan lines, the two capacitors are charged to a higher value than they would have without the equalizing pulses, but they both arrive at an identical voltage. The RC time constant offset that would have resulted in two different end point voltages is still there, but the identically timed pulses have overwhelmed it by adding charge. So, the ZERO is not really zero but some small millivolt level that is insignificant enough for the system to ignore. The important part is that the zero point is the same for both.
     
  9. benta

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    Dec 7, 2015
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    Don't think about it as duty cycle, but as charge time and discharge time. With proper selection of the charge resistor and discharge resistor (or ditto capacitors, depending on the design), the fact that the charge time during equalization is only half that of a real hsync, the gradual (pulsed) voltage decay shown in your picture will occur.

    It's a very old-fashioned way of detecting vsync, but useful for illustration.

    Benta.
     
  10. crutschow

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    Mar 14, 2008
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    As I and Kermit2 stated, that drawing is not accurate. The duty cycle is not different for the last pulse.
    Below is an LTspice simulation of the pulses through an RC filter after a half line interlace.
    (The RC time-constant was selected to give a response similar to that shown in your drawing during the horizontal syn interval).
    As you can see the voltage settles to it's final value after about two equalizing pulses (≈4.5 time constants).
    (About 32mV at the end of the equalizing period for the pulse and RC values shown).

    upload_2016-7-21_9-19-10.png
     
    Last edited: Jul 21, 2016
  11. benta

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    Dec 7, 2015
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    Yep, close.
    Only issue is the serration ("field sync") pulses should be 4.7 us low, not 2.35 us. And line period is 64 us, not 63.5
    Perhaps a new simulation run would bring us even closer?
    Thanks for your effort.

    Benta.
     
  12. crutschow

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    For color, the line period is 2/455 of the color burst frequency or approximately 63.556μs.
    Close enough?
    Below is the revised sim.
    Not much difference in the integrated sync signal.

    upload_2016-7-21_16-56-24.png
     
    Last edited: Jul 21, 2016
  13. crutschow

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    And once the voltage is within ± one electron charge, it's as close as you are going to get. ;)
     
  14. Papabravo

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    Semantically, a distinction without a difference
     
  15. crutschow

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    I disagree.
    You are talking theoretical mathematics, I am talking real world practice.
     
  16. Papabravo

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    And in the real world there are measurable and observable differences for a very long time as capacitors charge and discharge. Have you got the patience to wait long enough for the last unit of charge to move? I know I don't.
     
  17. Himanshoo

    Thread Starter Member

    Apr 3, 2015
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    can I have simulation without equalizing pulses....
     
  18. crutschow

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    Sure, but it's pointless.
    I though the discussion was about how the circuit responds with equalizing pulses. :confused:
    Without them the voltage will just decay to very near zero during that equalization time.
     
  19. crutschow

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    If it was a 1fF capacitor, I might. :rolleyes:
     
  20. Papabravo

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    Who knew the limits of your patience? Certainly not I.
     
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