Disassembler ?

Thread Starter

Mathematics!

Joined Jul 21, 2008
1,036
Ok I am trying to write a disassemblier for the PIC18

insruction set and registers are as follows
Rich (BB code):
nop         0000 0000 0000 0000
;nil         1111 pppp pppp pppp
addwf F,D,A 0010 01da ffff ffff
addwfc F,D,A 0010 00da ffff ffff
andwf F,D,A 0001 01da ffff ffff
clrf F,A 0110 101a ffff ffff
comf F,D,A 0001 11da ffff ffff
cpfseq F,A 0110 001a ffff ffff
cpfsgt F,A 0110 010a ffff ffff
cpfslt F,A 0110 000a ffff ffff
decf F,D,A 0000 01da ffff ffff
decfsz F,D,A 0010 11da ffff ffff
dcfsnz F,D,A 0100 11da ffff ffff
incf F,D,A 0010 10da ffff ffff
incfsz F,D,A 0011 11da ffff ffff
infsnz F,D,A 0100 10da ffff ffff
iorwf F,D,A 0001 00da ffff ffff
movf F,D,A 0101 00da ffff ffff
movff Y         1100 ffff ffff ffff
movwf F,A 0110 111a ffff ffff
mulwf F,A 0000 001a ffff ffff
negf F,A 0110 110a ffff ffff
rlcf F,D,A 0011 01da ffff ffff
rlncf F,D,A 0100 01da ffff ffff
rrcf F,D,A 0011 00da ffff ffff
rrncf F,D,A 0100 00da ffff ffff
setf F,A 0110 100a ffff ffff
subfwb F,D,A 0101 01da ffff ffff
subwf F,D,A 0101 11da ffff ffff
subwfb F,D,A 0101 10da ffff ffff
swapf F,D,A 0011 10da ffff ffff
tstfsz F,A 0110 011a ffff ffff
xorwf F,D,A 0001 10da ffff ffff
bcf F,B,A 1001 bbba ffff ffff
bsf F,B,A 1000 bbba ffff ffff
btfsc F,B,A 1011 bbba ffff ffff
btfss F,B,A 1010 bbba ffff ffff
btg F,B,A 0111 bbba ffff ffff
bc N         1110 0010 nnnn nnnn
bn N         1110 0110 nnnn nnnn
bnc N         1110 0011 nnnn nnnn
bnn N         1110 0111 nnnn nnnn
bnov N         1110 0101 nnnn nnnn
bnz N         1110 0001 nnnn nnnn
bov N         1110 0100 nnnn nnnn
bra M         1101 0nnn nnnn nnnn
bz N         1110 0000 nnnn nnnn
call W         1110 110s kkkk kkkk
clrwdt         0000 0000 0000 0100
daw         0000 0000 0000 0111
goto W         1110 1111 kkkk kkkk
pop         0000 0000 0000 0110
push         0000 0000 0000 0101
rcall M         1101 1nnn nnnn nnnn
reset         0000 0000 1111 1111
retfie S 0000 0000 0001 000s
retlw K         0000 1100 kkkk kkkk
return S 0000 0000 0001 001s
sleep         0000 0000 0000 0011
addlw K         0000 1111 kkkk kkkk
andlw K         0000 1011 kkkk kkkk
iorlw K         0000 1001 kkkk kkkk
lfsr Z         1110 1110 00ff kkkk
movlb C         0000 0001 0000 kkkk
movlw K         0000 1110 kkkk kkkk
mullw K         0000 1101 kkkk kkkk
sublw K         0000 1000 kkkk kkkk
xorlw K         0000 1010 kkkk kkkk
tblrd*         0000 0000 0000 1000
tblrd*+         0000 0000 0000 1001
tblrd*-         0000 0000 0000 1010
tblrd+*         0000 0000 0000 1011
tblwt*         0000 0000 0000 1100
tblwt*+         0000 0000 0000 1101
tblwt*-         0000 0000 0000 1110
tblwt+*         0000 0000 0000 1111
Rich (BB code):
0FFF TOSU
0FFE TOSH
0FFD TOSL
0FFC STKPTR
0FFB PCLATU
0FFA PCLATH
0FF9 PCL
0FF8 TBLPTRU
0FF7 TBLPTRH
0FF6 TBLPTRL
0FF5 TABLAT
0FF4 PRODH
0FF3 PRODL
0FF2 INTCON
0FF1 INTCON2
0FF0 INTCON3
0FEF INDF0
0FEE POSTINC0
0FED POSTDEC0
0FEC PREINC0
0FEB PLUSW0
0FEA FSR0H
0FE9 FSR0L
0FE8 WREG
0FE7 INDF1
0FE6 POSTINC1
0FE5 POSTDEC1
0FE4 PREINC1
0FE3 PLUSW1
0FE2 FSR1H
0FE1 FSR1L
0FE0 BSR
0FDF INDF2
0FDE POSTINC2
0FDD POSTDEC2
0FDC PREINC2
0FDB PLUSW2
0FDA FSR2H
0FD9 FSR2L
0FD8 STATUS
0FD7 TMR0H
0FD6 TMR0L
0FD4 0FD4h
0FD5 T0CON
0FD3 OSCCON
0FD2 LVDCON
0FD1 WDTCON
0FD0 RCON
0FCF TMR1H
0FCE TMR1L
0FCD T1CON
0FCC TMR2
0FCB PR2
0FCA T2CON
0FC9 SSPBUF
0FC8 SSPADD
0FC7 SSPSTAT
0FC6 SSPCON1
0FC5 SSPCON2
0FC4 ADRESH
0FC3 ADRESL
0FC2 ADCON0
0FC1 ADCON1
0FC0 ADCON2
0FBF CCPR1H
0FBE CCPR1L
0FBD CCP1CON
0FBC CCPR2H
0FBB CCPR2L
0FBA CCP2CON
0FB9 CCPR3H
0FB8 CCPR3L
0FB7 CCP3CON
0FB6 0FB6h
0FB5 CVRCON
0FB4 CMCON
0FB3 TMR3H
0FB2 TMR3L
0FB1 T3CON
0FB0 PSPCON
0FAF SPBRG1
0FAE RCREG1
0FAD TXREG1
0FAC TXSTA1
0FAB RCSTA1
0FAA EEADRH
0FA9 EEADR
0FA8 EEDATA
0FA7 EECON2
0FA6 EECON1
0FA5 IPR3
0FA4 PIR3
0FA3 PIE3
0FA2 IPR2
0FA1 PIR2
0FA0 PIE2
0F9F IPR1
0F9E PIR1
0F9D PIE1
0F9C MEMCON
0F9B 0F9Bh
0F9A TRISJ
0F99 TRISH
0F98 TRISG
0F97 TRISF
0F96 TRISE
0F95 TRISD
0F94 TRISC
0F93 TRISB
0F92 TRISA
0F91 LATJ
0F90 LATH
0F8F LATG
0F8E LATF
0F8D LATE
0F8C LATD
0F8B LATC
0F8A LATB
0F89 LATA
0F88 PORTJ
0F87 PORTH
0F86 PORTG
0F85 PORTF
0F84 PORTE
0F83 PORTD
0F82 PORTC
0F81 PORTB
0F80 PORTA
I am confused about how to go about translating the hex file back into asm. Ok for every 4 character = 2 bytes = 1 instruction.

Should I convert this hex decemial instruction to binary and start comparing with the bit's of each instruction set until I get a match.

For instance say I have 2700 = 0010 0111 0000 0000 in binary
if you load an array of string values of the binary values for the opcodes.

For instance addwf F,D,A 0010 01da ffff ffff just have an array entry
"0010 01da ffff ffff".

Then is it just taking 0010 0111 0000 0000 and comparing bit by bit until you weed out the only one that fits.

Because I am just worried if any opcodes could have the same starting byte, If so then how many bits do I have to check before I know the correct opcode. Seems to me it would vary which makes this all the more harder.

It is easy when you have an opcode that has only one binary value. But my problem is I haven't found away to distingish between opcodes that have many binary values assoiated to them.

Any help or suggestions would be great.

0010 0111 0000 0000 => addwf 0 right? but what if the da = 00 instead of 11 How would i represent this differently


I guess I don't understand

Rich (BB code):
where:  f       register file address
                d       destination select:
                                (0, -> w), (1 -> f)
                                the letters w or f may be used
                                to select the destination
                s       destination select:
                                (0, -> f and w), (1, -> f)
                                the letters w or f may be used
                                to select the destination
                t       table byte select:
                                (0, -> lower byte)
                                (1, -> upper byte)
                i       table pointer control
                                (0, -> no change)
                                (1, -> post increment)
                b       bit address of an 8-bit file register
                p       peripheral register file address
                k       literal constant
                label   label name
So for addwf would I write for when it is da =00 as opposed to 11?

I now get f means register , k is constant but I am confused how to display the difference in d a b s when dissasemblying?

I figured out how I am going to disassembly basically look for full matches first and go to smaller and smaller sizes...etc
For example it will try to match with
Rich (BB code):
tblrd*         0000 0000 0000 1000
tblrd*+         0000 0000 0000 1001
tblrd*-         0000 0000 0000 1010
tblrd+*         0000 0000 0000 1011
tblwt*         0000 0000 0000 1100
tblwt*+         0000 0000 0000 1101
tblwt*-         0000 0000 0000 1110
tblwt+*         0000 0000 0000 1111
first then go to the next biggest , something like match the first 10 chars then to the first 8 char ,...etc
Rich (BB code):
lfsr Z         1110 1110 00ff kkkk
But what to do with d a b s ??
 
Last edited:

n9352527

Joined Oct 14, 2005
1,198
I think the easiest way is to filter the instructions into groups based on the first x bits of coding. E.g. bsf, bcf, btfsc, btfss (a group with 4 bits coding and bbba + f) all start with 10.

Apply similar logic to filter the rest of the groups, and then continue filtering a group further based on the rest of the bits. E.g. bsf is xx00, bcf is xx01 etc.
 

Thread Starter

Mathematics!

Joined Jul 21, 2008
1,036
Yes , I just figured out a good way of doing that.

Try to match all 16 bit fix instructions first (such as tblwt+* 0000 0000 0000 1111) if not successful then try matching the first 10 bit's , and so on until a match is found or invalid opcode...

But my problem is something like this
Rich (BB code):
0010 0111 ffff ffff
0010 0110 ffff ffff
0010 0101 ffff ffff
0010 0100 ffff ffff
addwf F,D,A 0010 01da ffff ffff

They are all addwf but for displaying purposes what is the difference?
I just don't get how to take care of d , a ...etc bits.

I am fine with f , k .
 

n9352527

Joined Oct 14, 2005
1,198
You realise of course that the d is the destination and a is the RAM access bit. So, the example above would be, if we defined F (dest F) as 1, W (dest W) as 0, A (Access RAM) as 0 and B (BSR bank select) as 1, represented in mnemonics:

addwf REG, F, B
addwf REG, F, A
addwf REG, W, B
addwf REG, W, A

Or, you have to decode the RAM access bit into the REG address name, for example a = 0 is RAM access address names. a= 1, then the REG name would be selected from the value in BSR.

addwf BSRSELECTED, F
addwf RAMACCESS, F
addwf BSRSELECTED, W
addwf RAMACCESS, W
 
Last edited:

Thread Starter

Mathematics!

Joined Jul 21, 2008
1,036
I don't fully under stand .

So what would be the display for the four instructions
Rich (BB code):
0010 0111 ffff ffff
0010 0110 ffff ffff
0010 0101 ffff ffff
0010 0100 ffff ffff
addwf only takes 2 operands so why do they display addwf REG,F,B

And d = 0 means that the first operand contents are moved into the seconf operand ???
And d = 1 is the opposite ?

The a = 0 or 1 , (acess ram ) is this just a= 0 means it is from memory [varible] ??

I don't get the distinction
BSRSELECTED, RAMACCESS are these key words?

ffff ffff means register so why do you even need to decode the RAM access bit into the REG address name. I would just take the value of ffff ffff and lookup the corosponding register ?

When I see code.
It only looks like
Rich (BB code):
addwf arg1, arg2
not 3 arguments
Rich (BB code):
addwf REG, F, B
I guess I just don't get how to fully read opcode mnemonics
 
Last edited:

Thread Starter

Mathematics!

Joined Jul 21, 2008
1,036
Also ffff ffff is a 8 bit number the registers are 16 bits
Rich (BB code):
0FF9 PCL  = 1111 1111 1001
how can this fit in ffff ffff?

Could we go thru a few examples like what would be the machine code for


addwf 1 ,f
addwf 1 ,w

is the
 
Last edited:

beenthere

Joined Apr 20, 2004
15,819
FFFF FFFF is a 32 bit number.

Hexidecimal - Binary

0 - 0000
1 - 0001
2 - 0010
3 - 0011
4 - 0100
5 - 0101
6 - 0110
7 - 0111
8 - 1000
9 - 1001
A - 1010
B - 1011
C - 1100
D - 1101
E - 1110
F - 1111

If you have the instruction set for the PIC you are working with, the code for those two instructions will be in it.

It is much easier to do a disassembler if you have first written an assembler.
 

Thread Starter

Mathematics!

Joined Jul 21, 2008
1,036
Yes but I have the format of the opcode as
Rich (BB code):
0010 01da ffff ffff
d = 0 or 1 it is a destination bit
a = 0 or 1 it is a acess ram bit

I would think they mean ffff ffff is a 8 bits = 1 byte. Thought f stands for it had to be a register?

If they mean ffff ffffh then
Rich (BB code):
0010 01da ffff ffff
would be a 40 bit instruction or a 64 bit instruction depending on how you look at 0010 01da either 4 bytes or as 8 bits ???

I know hex for FFFF FFFF h is a different story.
But look up a few post I give all the registers and opcodes.
They are representing the registers as 2 hex values = 2 bytes = max of 65535 in dec = 1111 1111 1111 1111 in binary.

These are PIC 18 instruction.
So I think they are 16 bit instruction set but even if it where 32 bit instruction set it still isn't 40?
 

beenthere

Joined Apr 20, 2004
15,819
The instruction set will explicitly give the format for every command. There are command that are contained in one op code, like INC A. There are others that will need a value or appended address, like STA $FE00.

Those are 6502 instructions, by the way. Don't be confused.
 

Thread Starter

Mathematics!

Joined Jul 21, 2008
1,036
I am pretty sure I got all the opcodes correct up above.

http://freedatasheets.com/downloads/%22PIC18%20%200.25%20Micron%20%20Ethernet%20%20EMB%20%20MSSP%20%20EUSART%20%20PIC18F97J60%20%20PIC18F87J60%20%20PIC18F67J60%22.pdf

and ffff ffff is 8 bits = 1 bytes each f is 1 bit.

So then my only question is how does the 2 byte registers fit into the one bit ffff ffff. The registers have to be between 0- 256 in dec

But we have stuff like 0FF1 ?
Is their a difference in file register and register because this is the only guess.

And it differ's also from this http://e-tradition.net/bytes/6502/6502_instruction_set.html
 
Last edited:

beenthere

Joined Apr 20, 2004
15,819
This is all made abundantly clear by close reading of the data sheet. The PDF (39760d from Microchip) explains all, beginning at section 19.1.

By the way, have you though about how to deal with tables and data that will not disassemble? You will run into them.
 

n9352527

Joined Oct 14, 2005
1,198
Take a register at RAM access area, e.g. 0x00, and storing the result to W reg, the instruction would be:

0010 0100 0000 0000 (addwf 0x00, W)

IF the register is not in RAM access area, e.g. 0xE0, similarly storing the result to W reg, the instruction is:

0010 0101 1110 0000 (addwf 0xE0, W)

Notice the difference. In the second case, the BSR had to be set accordingly to point to the correct bank prior to execution. Check whether the MPASM generates the banking code automatically or not, and adjust your disassembler accordingly.

The a bit determines whether the register f is in RAM access area or not.
 

n9352527

Joined Oct 14, 2005
1,198
The register in RAM access is 256 bytes, which fit in a byte addressing (a = 0, f = address). Other registers use lower nibble of BSR as MSB of the address. Thus allowing address like 0xF34 to be accessed (a = 1, BSR = 0x0F, f = 0x34).
 

Thread Starter

Mathematics!

Joined Jul 21, 2008
1,036
Rich (BB code):
0010 0100 0000 0000 (addwf 0x00, W)
Rich (BB code):
addwf F,D,A 0010 01da ffff ffff
I was just writing it out like
addwf ffff ffff , 0 , 0

I thought you just substitute?

So is it always (D=0) => write a w for the D place and D = 1 write a f in the D place?

As for (a = 0) => f is an address that is a number from 0 to 256
(a = 1) allows you to access the registers
Rich (BB code):
0FFF TOSU
0FFE TOSH
0FFD TOSL
0FFC STKPTR
0FFB PCLATU
0FFA PCLATH
0FF9 PCL
0FF8 TBLPTRU
0FF7 TBLPTRH
0FF6 TBLPTRL
0FF5 TABLAT
0FF4 PRODH
0FF3 PRODL
0FF2 INTCON
0FF1 INTCON2
0FF0 INTCON3
0FEF INDF0
0FEE POSTINC0
0FED POSTDEC0
0FEC PREINC0
0FEB PLUSW0
0FEA FSR0H
0FE9 FSR0L
0FE8 WREG
0FE7 INDF1
0FE6 POSTINC1
0FE5 POSTDEC1
0FE4 PREINC1
0FE3 PLUSW1
0FE2 FSR1H
0FE1 FSR1L
0FE0 BSR
0FDF INDF2
0FDE POSTINC2
0FDD POSTDEC2
0FDC PREINC2
0FDB PLUSW2
0FDA FSR2H
0FD9 FSR2L
0FD8 STATUS
0FD7 TMR0H
0FD6 TMR0L
0FD4 0FD4h
0FD5 T0CON
0FD3 OSCCON
0FD2 LVDCON
0FD1 WDTCON
0FD0 RCON
0FCF TMR1H
0FCE TMR1L
0FCD T1CON
0FCC TMR2
0FCB PR2
0FCA T2CON
0FC9 SSPBUF
0FC8 SSPADD
0FC7 SSPSTAT
0FC6 SSPCON1
0FC5 SSPCON2
0FC4 ADRESH
0FC3 ADRESL
0FC2 ADCON0
0FC1 ADCON1
0FC0 ADCON2
0FBF CCPR1H
0FBE CCPR1L
0FBD CCP1CON
0FBC CCPR2H
0FBB CCPR2L
0FBA CCP2CON
0FB9 CCPR3H
0FB8 CCPR3L
0FB7 CCP3CON
0FB6 0FB6h
0FB5 CVRCON
0FB4 CMCON
0FB3 TMR3H
0FB2 TMR3L
0FB1 T3CON
0FB0 PSPCON
0FAF SPBRG1
0FAE RCREG1
0FAD TXREG1
0FAC TXSTA1
0FAB RCSTA1
0FAA EEADRH
0FA9 EEADR
0FA8 EEDATA
0FA7 EECON2
0FA6 EECON1
0FA5 IPR3
0FA4 PIR3
0FA3 PIE3
0FA2 IPR2
0FA1 PIR2
0FA0 PIE2
0F9F IPR1
0F9E PIR1
0F9D PIE1
0F9C MEMCON
0F9B 0F9Bh
0F9A TRISJ
0F99 TRISH
0F98 TRISG
0F97 TRISF
0F96 TRISE
0F95 TRISD
0F94 TRISC
0F93 TRISB
0F92 TRISA
0F91 LATJ
0F90 LATH
0F8F LATG
0F8E LATF
0F8D LATE
0F8C LATD
0F8B LATC
0F8A LATB
0F89 LATA
0F88 PORTJ
0F87 PORTH
0F86 PORTG
0F85 PORTF
0F84 PORTE
0F83 PORTD
0F82 PORTC
0F81 PORTB
0F80 PORTA
Don't really get what BSR is and how to determine it's value seems like it would always have to be 0F???
What is the BSR ?

Anyway let see if I got these bits straight
a = 0 is for accessing ram registers
a = 1 is to access a register not in ram like above register list
d = 0 means use w register W
d = 1 means use f register F
k = a constant
s ???
b ???
n ???
 

n9352527

Joined Oct 14, 2005
1,198
Ok, you get most of it. Let's get the terminology straight,

a = 0 is for accessing registers in Access RAM area.
a = 1 is for accessing registers in General Purpose RAM area.

They are both RAM.

BSR is a register, it is used as banking control. The way it works is the bits in BSR are used together with the address bits. E.g. BSR = 0x02, address 0x14, then the register address is 0x214. This way, the controller can access more than 256 bytes of RAM with only one byte address.

Note that usually the RAM access area is mapped to two disjointed segments, the first is from 0x00 to 0x7F and the second is from 0xF80 to 0xFFF (your example above). This area does not need the BSR register. They are mapped as 0x00 to 0xFF. Other RAM areas need the BSR. BSR = 0x00 and address = 0x80 point to first bank at 0x80.

Have a look in the datasheet for the Memory Map, the banks and the RAM access arrangements and addresses. You'd get the idea.

s = controls the shadow registers for fast call/return. Refer to the shadow registers in datasheet.

b = bit selector. Points to a particular bit in a byte (0x00 to 0x07).

n = the address for call/branch. Can be relative (2's complement) or absolute.

If in doubt, try coding simple programs to test few cases and observe the resulting codes. It'd be straightforward to deduce the hows and whats.
 

Thread Starter

Mathematics!

Joined Jul 21, 2008
1,036
Rich (BB code):
return S       0000 0000 0001 001s
call    W       1110 110s kkkk  kkkk
retfie  S       0000 0000 0001 000s
So if s = 0 or 1 what is the differences in displaying
is it just

retfie 1 if s = 1
retfie 0 if s = 0

return 1 if s = 1
return 0 if s = 0

call W s = 0 or s = 1 what do you write for these ???

Question 2
The b is bit selector but how is the 0 , 1, 2,3,4,5,6,7 displayed differently for instructions like

Rich (BB code):
bcf F,B,A 1001 bbba ffff ffff
bsf F,B,A 1000 bbba ffff ffff
btfsc F,B,A 1011 bbba ffff ffff
btfss F,B,A 1010 bbba ffff ffff
btg F,B,A 0111 bbba ffff ffff
What would be displayed for something like
bcf F,B,A 1001 bbba ffff ffff where bbb = 7 = 111 or bbb = 0 = 000 etc ...

I don't really get bit selector what is this actually doing is it selecting a memory address greater then FFh or what. Why the distinction between b and f.

Question 3
Rich (BB code):
bra M         1101 0nnn nnnn nnnn
Should the M be N ? And n = the address for call/branch
So do I just substitute the nnn nnnn nnnn in for M this must be a number from 0 - 7FFh. Maybe I am not correct about the straight substitution.

Question 4
Last thing is
Rich (BB code):
lfsr Z         1110 1110 00ff kkkk
movlb C        0000 0001 0000 kkkk
goto W         1110 1111 kkkk kkkk
rcall M        1101 1nnn nnnn nnnn
bra M          1101 0nnn nnnn nnnn
movff Y        1100 ffff ffff ffff
For these instructions the capital letters for the operands of the mnemonics don't corrospond to the lower case n ,k , f...
Should the Z , C , W , M ,... be k,k ,k,n,n,f ? Is Z = ff kkkk in lfsr Z ?

I think if I get these questions down I will be all set.
Thanks for all your help.
 

n9352527

Joined Oct 14, 2005
1,198
IF you define FAST as 1, then to use fast call with shadow registers (s = 1):

call addr, FAST
return FAST
retfie FAST

Otherwise, with the default call scheme (s = 0):

call addr
return
retfie

Or, if you want you could explicitly state the s parameter:

call addr, 0
return 0
retfie 0


Bit selector, it select one particular bit in a byte. The byte is pointed by the register F. bbb selects one bit within register F. These instructions work on one bit, such as setting a bit, clearing a bit, testing a bit and so on.

1001 bbba ffff ffff
bcf F,B,A

1001 0110 [porta addr]
bcf PORTA, 0x03, 0

Note that the a parameter could be explicitly stated, or not (will use the default value). This is also valid for other instructions that use a parameter such as addwf, movf, etc.


BRA n
Make sure that you use 2's complement to calculate the jumping destination. The address is a relative address (i.e. jumping n bytes forward or backward from current location). The range is from -0x400 to 0x3FF. The minus sign signifies jumping backwards. So, it is not actually from 0 to 0x7FF.


lfsr is a two bytes instruction,

1110 1110 00ff kkkk (MSB)
1111 0000 kkkk kkkk (LSB)
lfsr f, k
lsfr 2, 0x23F

Load 0x02 to FSR2H and 0x3F to FSR2L.


movlb loads the 8 bits literal k to BSR. Check the code again, it should be:

0000 0001 kkkk kkkk
0000 0001 0100 1111
movlb 0x4F


goto W is also a two bytes instruction (W is 20 bits value):

1110 1111 kkkk kkkk (LSB, low 8 bits)
1111 kkkk kkkk kkkk (MSB, high 12 bits)

goto k
goto 0x54299


rcall is similar to bra, but pushing the PC to stack. Just replace M with n.


movff is a register to register copy without banking. It is a two bytes instruction with full two 12 bits addresses:

1100 ffff ffff ffff (source f address)
1111 ffff ffff ffff (destination f address)
mov 0x3F4, 0x4EE
 

Thread Starter

Mathematics!

Joined Jul 21, 2008
1,036
movff Y 1100 ffff ffff ffff

So you can just write out the btg 0 , 0 , 0 ( 3 operands and have it compile fine with mpasm.) But I see alot of people's source code with only 2 arguments to some of the 3 argument address like bcf. I would like to make my disassemblier the most readable as possible.

Right now I just write out the 3 operand display for it such as
btg 0,0,0 = 0111 0000 0000 0000.
For
Rich (BB code):
btg F,B,A      0111 bbba ffff ffff
That is why I am trying to understand the switches .
Basically I know ram access => means a bit .
d = destination either w , or f
b = not fully known ? b = 0 - 7 numbers but are these for selecting something and what would be an example of displaying it nicely.
f = register number (write out number unless ram access bit is set then write register if bsr = 0F )
k = constant (just write out number)
s = fast or not ( write FAST if s = 1 and nothing if s = 0 )
n = is their any difference between this and a constant value for display?
( think the best you can do is just write the hex value for the nnn nnnn nnnn )

I guess they should have named M = N if they where staying consistant
then I believe it is just substituting nnn nnnn nnnn value in for N.
Rich (BB code):
rcall M        1101 1nnn nnnn nnnn
Thanks for all your help.
I got it working so far with writing the 3 operand version . But now I am trying to make it pretty.
 

n9352527

Joined Oct 14, 2005
1,198
I don't think there is an alternative to make it pretty. If it requires three operands and that's how it should be. The two operands version is because the third operand can be omitted when it is equal to the default value. Otherwise, it should be explicitly stated.

The bit selector (b) is to select one particular bit in a byte. E.g. bsf command operating on a register value of 1110 1111, with b = 4, will set only the fourth bit in that register (value 0 to value 1). So, b selects one particular bit in a byte.

The standard way is to just display the bit select number for general purpose registers and display the bit name for special function registers. E.g.:

bcf 0x34, 0x04
bcf T0CON, TMR0ON

The second instruction operates on T0CON register and clear the TMR0ON bit (7). Of course, for GPR you could always define the bit name during coding and end-up with pretty meaningful code. Something like, ERRFLG = 0x34, PARERR = 0x04 and end up with:

bcf ERRFLG, PARERR instead of bcf 0x34, 4

However it would hard to do this and come up with something meaningful and contextual when disassembling.
 
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