1. Mathematics!

    Thread Starter Senior Member

    Jul 21, 2008
    1,022
    4
    Ok I am trying to write a disassemblier for the PIC18

    insruction set and registers are as follows
    Code ( (Unknown Language)):
    1.  
    2. nop         0000 0000 0000 0000
    3. ;nil         1111 pppp pppp pppp
    4. addwf F,D,A 0010 01da ffff ffff
    5. addwfc F,D,A 0010 00da ffff ffff
    6. andwf F,D,A 0001 01da ffff ffff
    7. clrf F,A 0110 101a ffff ffff
    8. comf F,D,A 0001 11da ffff ffff
    9. cpfseq F,A 0110 001a ffff ffff
    10. cpfsgt F,A 0110 010a ffff ffff
    11. cpfslt F,A 0110 000a ffff ffff
    12. decf F,D,A 0000 01da ffff ffff
    13. decfsz F,D,A 0010 11da ffff ffff
    14. dcfsnz F,D,A 0100 11da ffff ffff
    15. incf F,D,A 0010 10da ffff ffff
    16. incfsz F,D,A 0011 11da ffff ffff
    17. infsnz F,D,A 0100 10da ffff ffff
    18. iorwf F,D,A 0001 00da ffff ffff
    19. movf F,D,A 0101 00da ffff ffff
    20. movff Y         1100 ffff ffff ffff
    21. movwf F,A 0110 111a ffff ffff
    22. mulwf F,A 0000 001a ffff ffff
    23. negf F,A 0110 110a ffff ffff
    24. rlcf F,D,A 0011 01da ffff ffff
    25. rlncf F,D,A 0100 01da ffff ffff
    26. rrcf F,D,A 0011 00da ffff ffff
    27. rrncf F,D,A 0100 00da ffff ffff
    28. setf F,A 0110 100a ffff ffff
    29. subfwb F,D,A 0101 01da ffff ffff
    30. subwf F,D,A 0101 11da ffff ffff
    31. subwfb F,D,A 0101 10da ffff ffff
    32. swapf F,D,A 0011 10da ffff ffff
    33. tstfsz F,A 0110 011a ffff ffff
    34. xorwf F,D,A 0001 10da ffff ffff
    35. bcf F,B,A 1001 bbba ffff ffff
    36. bsf F,B,A 1000 bbba ffff ffff
    37. btfsc F,B,A 1011 bbba ffff ffff
    38. btfss F,B,A 1010 bbba ffff ffff
    39. btg F,B,A 0111 bbba ffff ffff
    40. bc N         1110 0010 nnnn nnnn
    41. bn N         1110 0110 nnnn nnnn
    42. bnc N         1110 0011 nnnn nnnn
    43. bnn N         1110 0111 nnnn nnnn
    44. bnov N         1110 0101 nnnn nnnn
    45. bnz N         1110 0001 nnnn nnnn
    46. bov N         1110 0100 nnnn nnnn
    47. bra M         1101 0nnn nnnn nnnn
    48. bz N         1110 0000 nnnn nnnn
    49. call W         1110 110s kkkk kkkk
    50. clrwdt         0000 0000 0000 0100
    51. daw         0000 0000 0000 0111
    52. goto W         1110 1111 kkkk kkkk
    53. pop         0000 0000 0000 0110
    54. push         0000 0000 0000 0101
    55. rcall M         1101 1nnn nnnn nnnn
    56. reset         0000 0000 1111 1111
    57. retfie S 0000 0000 0001 000s
    58. retlw K         0000 1100 kkkk kkkk
    59. return S 0000 0000 0001 001s
    60. sleep         0000 0000 0000 0011
    61. addlw K         0000 1111 kkkk kkkk
    62. andlw K         0000 1011 kkkk kkkk
    63. iorlw K         0000 1001 kkkk kkkk
    64. lfsr Z         1110 1110 00ff kkkk
    65. movlb C         0000 0001 0000 kkkk
    66. movlw K         0000 1110 kkkk kkkk
    67. mullw K         0000 1101 kkkk kkkk
    68. sublw K         0000 1000 kkkk kkkk
    69. xorlw K         0000 1010 kkkk kkkk
    70. tblrd*         0000 0000 0000 1000
    71. tblrd*+         0000 0000 0000 1001
    72. tblrd*-         0000 0000 0000 1010
    73. tblrd+*         0000 0000 0000 1011
    74. tblwt*         0000 0000 0000 1100
    75. tblwt*+         0000 0000 0000 1101
    76. tblwt*-         0000 0000 0000 1110
    77. tblwt+*         0000 0000 0000 1111
    78.  
    79.  
    Code ( (Unknown Language)):
    1. 0FFF TOSU
    2. 0FFE TOSH
    3. 0FFD TOSL
    4. 0FFC STKPTR
    5. 0FFB PCLATU
    6. 0FFA PCLATH
    7. 0FF9 PCL
    8. 0FF8 TBLPTRU
    9. 0FF7 TBLPTRH
    10. 0FF6 TBLPTRL
    11. 0FF5 TABLAT
    12. 0FF4 PRODH
    13. 0FF3 PRODL
    14. 0FF2 INTCON
    15. 0FF1 INTCON2
    16. 0FF0 INTCON3
    17. 0FEF INDF0
    18. 0FEE POSTINC0
    19. 0FED POSTDEC0
    20. 0FEC PREINC0
    21. 0FEB PLUSW0
    22. 0FEA FSR0H
    23. 0FE9 FSR0L
    24. 0FE8 WREG
    25. 0FE7 INDF1
    26. 0FE6 POSTINC1
    27. 0FE5 POSTDEC1
    28. 0FE4 PREINC1
    29. 0FE3 PLUSW1
    30. 0FE2 FSR1H
    31. 0FE1 FSR1L
    32. 0FE0 BSR
    33. 0FDF INDF2
    34. 0FDE POSTINC2
    35. 0FDD POSTDEC2
    36. 0FDC PREINC2
    37. 0FDB PLUSW2
    38. 0FDA FSR2H
    39. 0FD9 FSR2L
    40. 0FD8 STATUS
    41. 0FD7 TMR0H
    42. 0FD6 TMR0L
    43. 0FD4 0FD4h
    44. 0FD5 T0CON
    45. 0FD3 OSCCON
    46. 0FD2 LVDCON
    47. 0FD1 WDTCON
    48. 0FD0 RCON
    49. 0FCF TMR1H
    50. 0FCE TMR1L
    51. 0FCD T1CON
    52. 0FCC TMR2
    53. 0FCB PR2
    54. 0FCA T2CON
    55. 0FC9 SSPBUF
    56. 0FC8 SSPADD
    57. 0FC7 SSPSTAT
    58. 0FC6 SSPCON1
    59. 0FC5 SSPCON2
    60. 0FC4 ADRESH
    61. 0FC3 ADRESL
    62. 0FC2 ADCON0
    63. 0FC1 ADCON1
    64. 0FC0 ADCON2
    65. 0FBF CCPR1H
    66. 0FBE CCPR1L
    67. 0FBD CCP1CON
    68. 0FBC CCPR2H
    69. 0FBB CCPR2L
    70. 0FBA CCP2CON
    71. 0FB9 CCPR3H
    72. 0FB8 CCPR3L
    73. 0FB7 CCP3CON
    74. 0FB6 0FB6h
    75. 0FB5 CVRCON
    76. 0FB4 CMCON
    77. 0FB3 TMR3H
    78. 0FB2 TMR3L
    79. 0FB1 T3CON
    80. 0FB0 PSPCON
    81. 0FAF SPBRG1
    82. 0FAE RCREG1
    83. 0FAD TXREG1
    84. 0FAC TXSTA1
    85. 0FAB RCSTA1
    86. 0FAA EEADRH
    87. 0FA9 EEADR
    88. 0FA8 EEDATA
    89. 0FA7 EECON2
    90. 0FA6 EECON1
    91. 0FA5 IPR3
    92. 0FA4 PIR3
    93. 0FA3 PIE3
    94. 0FA2 IPR2
    95. 0FA1 PIR2
    96. 0FA0 PIE2
    97. 0F9F IPR1
    98. 0F9E PIR1
    99. 0F9D PIE1
    100. 0F9C MEMCON
    101. 0F9B 0F9Bh
    102. 0F9A TRISJ
    103. 0F99 TRISH
    104. 0F98 TRISG
    105. 0F97 TRISF
    106. 0F96 TRISE
    107. 0F95 TRISD
    108. 0F94 TRISC
    109. 0F93 TRISB
    110. 0F92 TRISA
    111. 0F91 LATJ
    112. 0F90 LATH
    113. 0F8F LATG
    114. 0F8E LATF
    115. 0F8D LATE
    116. 0F8C LATD
    117. 0F8B LATC
    118. 0F8A LATB
    119. 0F89 LATA
    120. 0F88 PORTJ
    121. 0F87 PORTH
    122. 0F86 PORTG
    123. 0F85 PORTF
    124. 0F84 PORTE
    125. 0F83 PORTD
    126. 0F82 PORTC
    127. 0F81 PORTB
    128. 0F80 PORTA
    I am confused about how to go about translating the hex file back into asm. Ok for every 4 character = 2 bytes = 1 instruction.

    Should I convert this hex decemial instruction to binary and start comparing with the bit's of each instruction set until I get a match.

    For instance say I have 2700 = 0010 0111 0000 0000 in binary
    if you load an array of string values of the binary values for the opcodes.

    For instance addwf F,D,A 0010 01da ffff ffff just have an array entry
    "0010 01da ffff ffff".

    Then is it just taking 0010 0111 0000 0000 and comparing bit by bit until you weed out the only one that fits.

    Because I am just worried if any opcodes could have the same starting byte, If so then how many bits do I have to check before I know the correct opcode. Seems to me it would vary which makes this all the more harder.

    It is easy when you have an opcode that has only one binary value. But my problem is I haven't found away to distingish between opcodes that have many binary values assoiated to them.

    Any help or suggestions would be great.

    0010 0111 0000 0000 => addwf 0 right? but what if the da = 00 instead of 11 How would i represent this differently


    I guess I don't understand

    Code ( (Unknown Language)):
    1.  
    2. where:  f       register file address
    3.                 d       destination select:
    4.                                 (0, -> w), (1 -> f)
    5.                                 the letters w or f may be used
    6.                                 to select the destination
    7.                 s       destination select:
    8.                                 (0, -> f and w), (1, -> f)
    9.                                 the letters w or f may be used
    10.                                 to select the destination
    11.                 t       table byte select:
    12.                                 (0, -> lower byte)
    13.                                 (1, -> upper byte)
    14.                 i       table pointer control
    15.                                 (0, -> no change)
    16.                                 (1, -> post increment)
    17.                 b       bit address of an 8-bit file register
    18.                 p       peripheral register file address
    19.                 k       literal constant
    20.                 label   label name
    21.  
    22.  
    So for addwf would I write for when it is da =00 as opposed to 11?

    I now get f means register , k is constant but I am confused how to display the difference in d a b s when dissasemblying?

    I figured out how I am going to disassembly basically look for full matches first and go to smaller and smaller sizes...etc
    For example it will try to match with
    Code ( (Unknown Language)):
    1.  
    2. tblrd*         0000 0000 0000 1000
    3. tblrd*+         0000 0000 0000 1001
    4. tblrd*-         0000 0000 0000 1010
    5. tblrd+*         0000 0000 0000 1011
    6. tblwt*         0000 0000 0000 1100
    7. tblwt*+         0000 0000 0000 1101
    8. tblwt*-         0000 0000 0000 1110
    9. tblwt+*         0000 0000 0000 1111
    10.  
    first then go to the next biggest , something like match the first 10 chars then to the first 8 char ,...etc
    Code ( (Unknown Language)):
    1. lfsr Z         1110 1110 00ff kkkk
    But what to do with d a b s ??
     
    Last edited: Dec 9, 2008
  2. n9352527

    AAC Fanatic!

    Oct 14, 2005
    1,198
    4
    I think the easiest way is to filter the instructions into groups based on the first x bits of coding. E.g. bsf, bcf, btfsc, btfss (a group with 4 bits coding and bbba + f) all start with 10.

    Apply similar logic to filter the rest of the groups, and then continue filtering a group further based on the rest of the bits. E.g. bsf is xx00, bcf is xx01 etc.
     
  3. Mathematics!

    Thread Starter Senior Member

    Jul 21, 2008
    1,022
    4
    Yes , I just figured out a good way of doing that.

    Try to match all 16 bit fix instructions first (such as tblwt+* 0000 0000 0000 1111) if not successful then try matching the first 10 bit's , and so on until a match is found or invalid opcode...

    But my problem is something like this
    Code ( (Unknown Language)):
    1.  
    2. 0010 0111 ffff ffff
    3. 0010 0110 ffff ffff
    4. 0010 0101 ffff ffff
    5. 0010 0100 ffff ffff
    6.  
    addwf F,D,A 0010 01da ffff ffff

    They are all addwf but for displaying purposes what is the difference?
    I just don't get how to take care of d , a ...etc bits.

    I am fine with f , k .
     
  4. n9352527

    AAC Fanatic!

    Oct 14, 2005
    1,198
    4
    You realise of course that the d is the destination and a is the RAM access bit. So, the example above would be, if we defined F (dest F) as 1, W (dest W) as 0, A (Access RAM) as 0 and B (BSR bank select) as 1, represented in mnemonics:

    addwf REG, F, B
    addwf REG, F, A
    addwf REG, W, B
    addwf REG, W, A

    Or, you have to decode the RAM access bit into the REG address name, for example a = 0 is RAM access address names. a= 1, then the REG name would be selected from the value in BSR.

    addwf BSRSELECTED, F
    addwf RAMACCESS, F
    addwf BSRSELECTED, W
    addwf RAMACCESS, W
     
    Last edited: Dec 9, 2008
  5. Mathematics!

    Thread Starter Senior Member

    Jul 21, 2008
    1,022
    4
    I don't fully under stand .

    So what would be the display for the four instructions
    Code ( (Unknown Language)):
    1.  
    2. 0010 0111 ffff ffff
    3. 0010 0110 ffff ffff
    4. 0010 0101 ffff ffff
    5. 0010 0100 ffff ffff
    6.  
    addwf only takes 2 operands so why do they display addwf REG,F,B

    And d = 0 means that the first operand contents are moved into the seconf operand ???
    And d = 1 is the opposite ?

    The a = 0 or 1 , (acess ram ) is this just a= 0 means it is from memory [varible] ??

    I don't get the distinction
    BSRSELECTED, RAMACCESS are these key words?

    ffff ffff means register so why do you even need to decode the RAM access bit into the REG address name. I would just take the value of ffff ffff and lookup the corosponding register ?

    When I see code.
    It only looks like
    Code ( (Unknown Language)):
    1. addwf arg1, arg2
    not 3 arguments
    Code ( (Unknown Language)):
    1. addwf REG, F, B
    I guess I just don't get how to fully read opcode mnemonics
     
    Last edited: Dec 9, 2008
  6. Mathematics!

    Thread Starter Senior Member

    Jul 21, 2008
    1,022
    4
    Also ffff ffff is a 8 bit number the registers are 16 bits
    Code ( (Unknown Language)):
    1. 0FF9 PCL  = 1111 1111 1001
    how can this fit in ffff ffff?

    Could we go thru a few examples like what would be the machine code for


    addwf 1 ,f
    addwf 1 ,w

    is the
     
    Last edited: Dec 9, 2008
  7. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
    282
    FFFF FFFF is a 32 bit number.

    Hexidecimal - Binary

    0 - 0000
    1 - 0001
    2 - 0010
    3 - 0011
    4 - 0100
    5 - 0101
    6 - 0110
    7 - 0111
    8 - 1000
    9 - 1001
    A - 1010
    B - 1011
    C - 1100
    D - 1101
    E - 1110
    F - 1111

    If you have the instruction set for the PIC you are working with, the code for those two instructions will be in it.

    It is much easier to do a disassembler if you have first written an assembler.
     
  8. Mathematics!

    Thread Starter Senior Member

    Jul 21, 2008
    1,022
    4
    Yes but I have the format of the opcode as
    Code ( (Unknown Language)):
    1. 0010 01da ffff ffff
    d = 0 or 1 it is a destination bit
    a = 0 or 1 it is a acess ram bit

    I would think they mean ffff ffff is a 8 bits = 1 byte. Thought f stands for it had to be a register?

    If they mean ffff ffffh then
    Code ( (Unknown Language)):
    1. 0010 01da ffff ffff
    would be a 40 bit instruction or a 64 bit instruction depending on how you look at 0010 01da either 4 bytes or as 8 bits ???

    I know hex for FFFF FFFF h is a different story.
    But look up a few post I give all the registers and opcodes.
    They are representing the registers as 2 hex values = 2 bytes = max of 65535 in dec = 1111 1111 1111 1111 in binary.

    These are PIC 18 instruction.
    So I think they are 16 bit instruction set but even if it where 32 bit instruction set it still isn't 40?
     
  9. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
    282
    The instruction set will explicitly give the format for every command. There are command that are contained in one op code, like INC A. There are others that will need a value or appended address, like STA $FE00.

    Those are 6502 instructions, by the way. Don't be confused.
     
  10. Mathematics!

    Thread Starter Senior Member

    Jul 21, 2008
    1,022
    4
    I am pretty sure I got all the opcodes correct up above.

    http://freedatasheets.com/downloads/%22PIC18%20%200.25%20Micron%20%20Ethernet%20%20EMB%20%20MSSP%20%20EUSART%20%20PIC18F97J60%20%20PIC18F87J60%20%20PIC18F67J60%22.pdf

    and ffff ffff is 8 bits = 1 bytes each f is 1 bit.

    So then my only question is how does the 2 byte registers fit into the one bit ffff ffff. The registers have to be between 0- 256 in dec

    But we have stuff like 0FF1 ?
    Is their a difference in file register and register because this is the only guess.

    And it differ's also from this http://e-tradition.net/bytes/6502/6502_instruction_set.html
     
    Last edited: Dec 9, 2008
  11. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
    282
    This is all made abundantly clear by close reading of the data sheet. The PDF (39760d from Microchip) explains all, beginning at section 19.1.

    By the way, have you though about how to deal with tables and data that will not disassemble? You will run into them.
     
  12. n9352527

    AAC Fanatic!

    Oct 14, 2005
    1,198
    4
    Take a register at RAM access area, e.g. 0x00, and storing the result to W reg, the instruction would be:

    0010 0100 0000 0000 (addwf 0x00, W)

    IF the register is not in RAM access area, e.g. 0xE0, similarly storing the result to W reg, the instruction is:

    0010 0101 1110 0000 (addwf 0xE0, W)

    Notice the difference. In the second case, the BSR had to be set accordingly to point to the correct bank prior to execution. Check whether the MPASM generates the banking code automatically or not, and adjust your disassembler accordingly.

    The a bit determines whether the register f is in RAM access area or not.
     
  13. n9352527

    AAC Fanatic!

    Oct 14, 2005
    1,198
    4
    The register in RAM access is 256 bytes, which fit in a byte addressing (a = 0, f = address). Other registers use lower nibble of BSR as MSB of the address. Thus allowing address like 0xF34 to be accessed (a = 1, BSR = 0x0F, f = 0x34).
     
  14. Mathematics!

    Thread Starter Senior Member

    Jul 21, 2008
    1,022
    4
    Code ( (Unknown Language)):
    1. 0010 010[U]0[/U] 0000 0000 (addwf 0x00, W)
    Code ( (Unknown Language)):
    1. addwf F,D,A 0010 01da ffff ffff
    I was just writing it out like
    addwf ffff ffff , 0 , 0

    I thought you just substitute?

    So is it always (D=0) => write a w for the D place and D = 1 write a f in the D place?

    As for (a = 0) => f is an address that is a number from 0 to 256
    (a = 1) allows you to access the registers
    Code ( (Unknown Language)):
    1.  
    2. 0FFF TOSU
    3. 0FFE TOSH
    4. 0FFD TOSL
    5. 0FFC STKPTR
    6. 0FFB PCLATU
    7. 0FFA PCLATH
    8. 0FF9 PCL
    9. 0FF8 TBLPTRU
    10. 0FF7 TBLPTRH
    11. 0FF6 TBLPTRL
    12. 0FF5 TABLAT
    13. 0FF4 PRODH
    14. 0FF3 PRODL
    15. 0FF2 INTCON
    16. 0FF1 INTCON2
    17. 0FF0 INTCON3
    18. 0FEF INDF0
    19. 0FEE POSTINC0
    20. 0FED POSTDEC0
    21. 0FEC PREINC0
    22. 0FEB PLUSW0
    23. 0FEA FSR0H
    24. 0FE9 FSR0L
    25. 0FE8 WREG
    26. 0FE7 INDF1
    27. 0FE6 POSTINC1
    28. 0FE5 POSTDEC1
    29. 0FE4 PREINC1
    30. 0FE3 PLUSW1
    31. 0FE2 FSR1H
    32. 0FE1 FSR1L
    33. 0FE0 BSR
    34. 0FDF INDF2
    35. 0FDE POSTINC2
    36. 0FDD POSTDEC2
    37. 0FDC PREINC2
    38. 0FDB PLUSW2
    39. 0FDA FSR2H
    40. 0FD9 FSR2L
    41. 0FD8 STATUS
    42. 0FD7 TMR0H
    43. 0FD6 TMR0L
    44. 0FD4 0FD4h
    45. 0FD5 T0CON
    46. 0FD3 OSCCON
    47. 0FD2 LVDCON
    48. 0FD1 WDTCON
    49. 0FD0 RCON
    50. 0FCF TMR1H
    51. 0FCE TMR1L
    52. 0FCD T1CON
    53. 0FCC TMR2
    54. 0FCB PR2
    55. 0FCA T2CON
    56. 0FC9 SSPBUF
    57. 0FC8 SSPADD
    58. 0FC7 SSPSTAT
    59. 0FC6 SSPCON1
    60. 0FC5 SSPCON2
    61. 0FC4 ADRESH
    62. 0FC3 ADRESL
    63. 0FC2 ADCON0
    64. 0FC1 ADCON1
    65. 0FC0 ADCON2
    66. 0FBF CCPR1H
    67. 0FBE CCPR1L
    68. 0FBD CCP1CON
    69. 0FBC CCPR2H
    70. 0FBB CCPR2L
    71. 0FBA CCP2CON
    72. 0FB9 CCPR3H
    73. 0FB8 CCPR3L
    74. 0FB7 CCP3CON
    75. 0FB6 0FB6h
    76. 0FB5 CVRCON
    77. 0FB4 CMCON
    78. 0FB3 TMR3H
    79. 0FB2 TMR3L
    80. 0FB1 T3CON
    81. 0FB0 PSPCON
    82. 0FAF SPBRG1
    83. 0FAE RCREG1
    84. 0FAD TXREG1
    85. 0FAC TXSTA1
    86. 0FAB RCSTA1
    87. 0FAA EEADRH
    88. 0FA9 EEADR
    89. 0FA8 EEDATA
    90. 0FA7 EECON2
    91. 0FA6 EECON1
    92. 0FA5 IPR3
    93. 0FA4 PIR3
    94. 0FA3 PIE3
    95. 0FA2 IPR2
    96. 0FA1 PIR2
    97. 0FA0 PIE2
    98. 0F9F IPR1
    99. 0F9E PIR1
    100. 0F9D PIE1
    101. 0F9C MEMCON
    102. 0F9B 0F9Bh
    103. 0F9A TRISJ
    104. 0F99 TRISH
    105. 0F98 TRISG
    106. 0F97 TRISF
    107. 0F96 TRISE
    108. 0F95 TRISD
    109. 0F94 TRISC
    110. 0F93 TRISB
    111. 0F92 TRISA
    112. 0F91 LATJ
    113. 0F90 LATH
    114. 0F8F LATG
    115. 0F8E LATF
    116. 0F8D LATE
    117. 0F8C LATD
    118. 0F8B LATC
    119. 0F8A LATB
    120. 0F89 LATA
    121. 0F88 PORTJ
    122. 0F87 PORTH
    123. 0F86 PORTG
    124. 0F85 PORTF
    125. 0F84 PORTE
    126. 0F83 PORTD
    127. 0F82 PORTC
    128. 0F81 PORTB
    129. 0F80 PORTA
    130.  
    Don't really get what BSR is and how to determine it's value seems like it would always have to be 0F???
    What is the BSR ?

    Anyway let see if I got these bits straight
    a = 0 is for accessing ram registers
    a = 1 is to access a register not in ram like above register list
    d = 0 means use w register W
    d = 1 means use f register F
    k = a constant
    s ???
    b ???
    n ???
     
  15. n9352527

    AAC Fanatic!

    Oct 14, 2005
    1,198
    4
    Ok, you get most of it. Let's get the terminology straight,

    a = 0 is for accessing registers in Access RAM area.
    a = 1 is for accessing registers in General Purpose RAM area.

    They are both RAM.

    BSR is a register, it is used as banking control. The way it works is the bits in BSR are used together with the address bits. E.g. BSR = 0x02, address 0x14, then the register address is 0x214. This way, the controller can access more than 256 bytes of RAM with only one byte address.

    Note that usually the RAM access area is mapped to two disjointed segments, the first is from 0x00 to 0x7F and the second is from 0xF80 to 0xFFF (your example above). This area does not need the BSR register. They are mapped as 0x00 to 0xFF. Other RAM areas need the BSR. BSR = 0x00 and address = 0x80 point to first bank at 0x80.

    Have a look in the datasheet for the Memory Map, the banks and the RAM access arrangements and addresses. You'd get the idea.

    s = controls the shadow registers for fast call/return. Refer to the shadow registers in datasheet.

    b = bit selector. Points to a particular bit in a byte (0x00 to 0x07).

    n = the address for call/branch. Can be relative (2's complement) or absolute.

    If in doubt, try coding simple programs to test few cases and observe the resulting codes. It'd be straightforward to deduce the hows and whats.
     
  16. Mathematics!

    Thread Starter Senior Member

    Jul 21, 2008
    1,022
    4
    Code ( (Unknown Language)):
    1.  
    2. return S       0000 0000 0001 001s
    3. call    W       1110 110s kkkk  kkkk
    4. retfie  S       0000 0000 0001 000s
    5.  
    So if s = 0 or 1 what is the differences in displaying
    is it just

    retfie 1 if s = 1
    retfie 0 if s = 0

    return 1 if s = 1
    return 0 if s = 0

    call W s = 0 or s = 1 what do you write for these ???

    Question 2
    The b is bit selector but how is the 0 , 1, 2,3,4,5,6,7 displayed differently for instructions like

    Code ( (Unknown Language)):
    1.  
    2. bcf F,B,A 1001 bbba ffff ffff
    3. bsf F,B,A 1000 bbba ffff ffff
    4. btfsc F,B,A 1011 bbba ffff ffff
    5. btfss F,B,A 1010 bbba ffff ffff
    6. btg F,B,A 0111 bbba ffff ffff
    7.  
    What would be displayed for something like
    bcf F,B,A 1001 bbba ffff ffff where bbb = 7 = 111 or bbb = 0 = 000 etc ...

    I don't really get bit selector what is this actually doing is it selecting a memory address greater then FFh or what. Why the distinction between b and f.

    Question 3
    Code ( (Unknown Language)):
    1. bra M         1101 0nnn nnnn nnnn
    Should the M be N ? And n = the address for call/branch
    So do I just substitute the nnn nnnn nnnn in for M this must be a number from 0 - 7FFh. Maybe I am not correct about the straight substitution.

    Question 4
    Last thing is
    Code ( (Unknown Language)):
    1.  
    2. lfsr Z         1110 1110 00ff kkkk
    3. movlb C        0000 0001 0000 kkkk
    4. goto W         1110 1111 kkkk kkkk
    5. rcall M        1101 1nnn nnnn nnnn
    6. bra M          1101 0nnn nnnn nnnn
    7. movff Y        1100 ffff ffff ffff
    8.  
    For these instructions the capital letters for the operands of the mnemonics don't corrospond to the lower case n ,k , f...
    Should the Z , C , W , M ,... be k,k ,k,n,n,f ? Is Z = ff kkkk in lfsr Z ?

    I think if I get these questions down I will be all set.
    Thanks for all your help.
     
  17. n9352527

    AAC Fanatic!

    Oct 14, 2005
    1,198
    4
    IF you define FAST as 1, then to use fast call with shadow registers (s = 1):

    call addr, FAST
    return FAST
    retfie FAST

    Otherwise, with the default call scheme (s = 0):

    call addr
    return
    retfie

    Or, if you want you could explicitly state the s parameter:

    call addr, 0
    return 0
    retfie 0


    Bit selector, it select one particular bit in a byte. The byte is pointed by the register F. bbb selects one bit within register F. These instructions work on one bit, such as setting a bit, clearing a bit, testing a bit and so on.

    1001 bbba ffff ffff
    bcf F,B,A

    1001 0110 [porta addr]
    bcf PORTA, 0x03, 0

    Note that the a parameter could be explicitly stated, or not (will use the default value). This is also valid for other instructions that use a parameter such as addwf, movf, etc.


    BRA n
    Make sure that you use 2's complement to calculate the jumping destination. The address is a relative address (i.e. jumping n bytes forward or backward from current location). The range is from -0x400 to 0x3FF. The minus sign signifies jumping backwards. So, it is not actually from 0 to 0x7FF.


    lfsr is a two bytes instruction,

    1110 1110 00ff kkkk (MSB)
    1111 0000 kkkk kkkk (LSB)
    lfsr f, k
    lsfr 2, 0x23F

    Load 0x02 to FSR2H and 0x3F to FSR2L.


    movlb loads the 8 bits literal k to BSR. Check the code again, it should be:

    0000 0001 kkkk kkkk
    0000 0001 0100 1111
    movlb 0x4F


    goto W is also a two bytes instruction (W is 20 bits value):

    1110 1111 kkkk kkkk (LSB, low 8 bits)
    1111 kkkk kkkk kkkk (MSB, high 12 bits)

    goto k
    goto 0x54299


    rcall is similar to bra, but pushing the PC to stack. Just replace M with n.


    movff is a register to register copy without banking. It is a two bytes instruction with full two 12 bits addresses:

    1100 ffff ffff ffff (source f address)
    1111 ffff ffff ffff (destination f address)
    mov 0x3F4, 0x4EE
     
  18. Mathematics!

    Thread Starter Senior Member

    Jul 21, 2008
    1,022
    4
    movff Y 1100 ffff ffff ffff

    So you can just write out the btg 0 , 0 , 0 ( 3 operands and have it compile fine with mpasm.) But I see alot of people's source code with only 2 arguments to some of the 3 argument address like bcf. I would like to make my disassemblier the most readable as possible.

    Right now I just write out the 3 operand display for it such as
    btg 0,0,0 = 0111 0000 0000 0000.
    For
    Code ( (Unknown Language)):
    1. btg F,B,A      0111 bbba ffff ffff
    That is why I am trying to understand the switches .
    Basically I know ram access => means a bit .
    d = destination either w , or f
    b = not fully known ? b = 0 - 7 numbers but are these for selecting something and what would be an example of displaying it nicely.
    f = register number (write out number unless ram access bit is set then write register if bsr = 0F )
    k = constant (just write out number)
    s = fast or not ( write FAST if s = 1 and nothing if s = 0 )
    n = is their any difference between this and a constant value for display?
    ( think the best you can do is just write the hex value for the nnn nnnn nnnn )

    I guess they should have named M = N if they where staying consistant
    then I believe it is just substituting nnn nnnn nnnn value in for N.
    Code ( (Unknown Language)):
    1. rcall M        1101 1nnn nnnn nnnn
    Thanks for all your help.
    I got it working so far with writing the 3 operand version . But now I am trying to make it pretty.
     
  19. n9352527

    AAC Fanatic!

    Oct 14, 2005
    1,198
    4
    I don't think there is an alternative to make it pretty. If it requires three operands and that's how it should be. The two operands version is because the third operand can be omitted when it is equal to the default value. Otherwise, it should be explicitly stated.

    The bit selector (b) is to select one particular bit in a byte. E.g. bsf command operating on a register value of 1110 1111, with b = 4, will set only the fourth bit in that register (value 0 to value 1). So, b selects one particular bit in a byte.

    The standard way is to just display the bit select number for general purpose registers and display the bit name for special function registers. E.g.:

    bcf 0x34, 0x04
    bcf T0CON, TMR0ON

    The second instruction operates on T0CON register and clear the TMR0ON bit (7). Of course, for GPR you could always define the bit name during coding and end-up with pretty meaningful code. Something like, ERRFLG = 0x34, PARERR = 0x04 and end up with:

    bcf ERRFLG, PARERR instead of bcf 0x34, 4

    However it would hard to do this and come up with something meaningful and contextual when disassembling.
     
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