When trouble shooting a TTL logic circuit, what is the likely problem if a steady-sate input voltage is invalid?
I'm not sure what they mean by steady-state. Does it just mean constant DC voltage?
I also know that TTL voltage levels are:
0 - 0.8 = low
2 - 5.0 = high
So if the "steady-state" input voltage is not within the TTL range, then it would be invalid. But this answer seems too obvious. Any tips appreciated.
I'm not sure what they mean by steady-state. Does it just mean constant DC voltage?
I also know that TTL voltage levels are:
0 - 0.8 = low
2 - 5.0 = high
So if the "steady-state" input voltage is not within the TTL range, then it would be invalid. But this answer seems too obvious. Any tips appreciated.