Digital logic circuit

Discussion in 'Digital Circuit Design' started by elexito, Oct 26, 2011.

  1. elexito

    Thread Starter New Member

    Oct 26, 2011
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    Question:
    A sequential circuits has one input(X) and two ouputs(Z1 and Z2). An output Z1=1 occurs every time the input sequence 010 is complete, provided that the sequence 100 has never occurred. An output Z2=1 output has occurred, Z1= can never occur but not vice versa. Find a Mealy state graph and state table.

    Can I get help getting the right path to start.
     
  2. BMorse

    Senior Member

    Sep 26, 2009
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    elexito likes this.
  3. Georacer

    Moderator

    Nov 25, 2009
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