Digital Design problem

Discussion in 'The Projects Forum' started by ishaan3731, Mar 4, 2012.

  1. ishaan3731

    Thread Starter Member

    Jun 23, 2011
    43
    1
    My teacher has given me a design problem in digital electronics ,which i have to implement both on papers as well as practically.I have to design a wire transmission system that transmits words of 3 bit . Now i have to include a odd parity checking system at receiver end that checks the parity generated by the parity bit generator located at transmitter end.

    in all the transmitter transmits 4 bits( 1 bit for parity and 3 bit word).......

    please help as i dont know how to even start off with this ........
     
  2. hexreader

    Active Member

    Apr 16, 2011
    250
    82
    Why don't you make a guess at which type of logic devices are likely to the kind of job you talk about.

    Start with the transmitting 4 bit problem, then the 4 bit receiving problem.

    Worry about parity last.

    Will you be transmitting the data in parallel (4 wires + ground + control lines) or in serial (1 wire + ground + control lines) ?

    Are you allowed to use any logic device you choose? Or are you limited to simple gates and flip-flops ?
     
    Last edited: Mar 4, 2012
  3. ishaan3731

    Thread Starter Member

    Jun 23, 2011
    43
    1
    actually the main area of concern is the parity checking......
    I wud prefer parallel transmission......as its the easiest..... Sending 4 bits is not a tough job as i will be using mono switches which are kind of press and hold switches(that hold there positions once pressed).....but i have to transmit 3bits of word and one bit for parity..... and i dont have a single hint to that.
     
  4. hexreader

    Active Member

    Apr 16, 2011
    250
    82
    I would guess that there are parity generator and parity decode logic chips out there, but I have not looked, and I am guessing that your tutor would not give you a good mark if you did use them.

    Never designed parity generator or parity checker before, but combining 2 input XOR gates should do the job.

    I will leave you to work out how, as it is your homework.
     
    Last edited: Mar 4, 2012
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