# Digital Circuit Not Gate Question

Discussion in 'General Electronics Chat' started by TrevorP, Oct 23, 2008.

1. ### TrevorP Thread Starter Active Member

Dec 8, 2006
55
0
Hey,

I'm doing a digital circuits assignment right now and part of a circuit they give us has something like this:

Code ( (Unknown Language)):
1.
2.             Vcc (5V)
3.              _____
4.                |
5.                \
6.                / Resistor
7.                \
8.             |
9. A -----|>o-----|
10.                |
11. B -----|>o-----|----- G
12.
Where |>o is a NOT gate. (Sorry about the diagram I can't find a good Linux schematic editor.) Now what I need to do is figure out what G's output will be. Now when A and B are both LOW I think that G should be HIGH. The problem occurs when A or B goes HIGH or both of them are HIGH.

My guess is that when A goes HIGH zero volts are produced on the output of the NOT gate. So the Vcc must then drop across the Resistor. However, what happens to the HIGH being produced by the B not gate?

So far I have for a truth table:

A B G
-----------
0 0 1
0 1 ??
1 0 ??
1 1 0

Basically does the NOT gate act as a sink for all of the potential (this sounds weird) when either gate produces a LOW?

Thanks

2. ### mik3 Senior Member

Feb 4, 2008
4,846
63
This NOT gates must have open collector outputs as not to be destroyed.

This is the truth table

A B G
0 0 1
1 0 1
0 1 1
1 1 0

3. ### TrevorP Thread Starter Active Member

Dec 8, 2006
55
0
This is because if they didn't then they would have a huge current passing through them?

4. ### mik3 Senior Member

Feb 4, 2008
4,846
63
Yes, one of the two gates would be low and the other high so a significant amount of current would flow through them, overheat them and finally destroy them.

5. ### TrevorP Thread Starter Active Member

Dec 8, 2006
55
0
Great thanks!

6. ### steveb Senior Member

Jul 3, 2008
2,433
469

I agree with this, but would like to make an observation. In the old days (and probably still today in ICs) people would connect the output of gates together and create what they called a "wired -or" gate. This is similar. It is like a wired-or gate with inverting inputs. Then, by DeMorgan's theorem, it is equivalent to a nand gate. - Just another way to look at it.

May 16, 2005
5,072
6

8. ### Ron H AAC Fanatic!

Apr 14, 2005
7,050
657
If the inverter outputs are open collector (or open drain), then it's a NOR gate. Either input high drives the output low. Both inputs have to be low for the output to be high. It's only a NAND if we are talking about negative true logic.

9. ### steveb Senior Member

Jul 3, 2008
2,433
469
Yes, that's a good point. The presence of the pull-up resistor implies open collector outputs. Although, one could argue that open collector gates imply active low outputs for control signals. Either way, it's interesting to see a "wired-or" turn up in conversation.