difference between always and assign in verilog

Discussion in 'Homework Help' started by vead, Oct 29, 2013.

  1. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    I am confused I want to know what is difference between always and assign and where they use

    program 1st
    module and2gate (A,B,Y);
    input A,B;
    output Y;
    assign Y=A&B;
    endmodule

    program 2st
    module and2gate (A,B,Y);
    input A,B;
    output Y
    reg y
    always@(AorB);
    begin
    Y<=A&B;
    end
    endmodule

    which program is right please someone explain where we use always and assign syntax
     
  2. WBahn

    Moderator

    Mar 31, 2012
    17,720
    4,788
    (1) Please format your code so that it is readily readable. Putting it inside a CODE tag will help.

    (2) Describe what efforts you have made to answer this question and what you have found out thus far.
     
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