dff asynchronous reset question

Discussion in 'Homework Help' started by limbonic, Dec 3, 2012.

  1. limbonic

    Thread Starter New Member

    Jul 4, 2011
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    Hello, guys i read about d flip flops in cmos and asynchronous reset from Neil H. E. Weste 'CMOS VLSI Design' book and i dont unsterstand in the figure below why the nand gate has a clock signal and how we can implement a nand gate like this. I know how i can implement a simple nand gate in cmos but this nand gate has clock signals attached.

    [​IMG]


    edit: i just found what is a tri-state register:

    [​IMG]

    Is the above nand gate the same as the tri-state register. The equivalent circuit of a clocked nand gate is a nand gate and a transmision gate?

    I would appreciated if anyone could help me.
    Thanks
     
    Last edited: Dec 3, 2012
  2. WBahn

    Moderator

    Mar 31, 2012
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    It
    s better to think of it as a NAND gate with a three-state output instead of a "clocked" NAND gate. But, yes, those NAND gates have additional transistors to enable and disable the output. The purpose is to prevent contention between them and the other outputs on the same node. Another way of dealing with contention, and reducing transistor count, is to size the transistors so that the drivers that are intended to change a state are sufficiently stronger than the transistors that are only meant to hold the state. But that requires a lot more care and simulation over process corners to make it reliable.
     
  3. limbonic

    Thread Starter New Member

    Jul 4, 2011
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    Thank you, i make the figure above and i think with the correct rationing of the transistors is equivalent to a DFF with asynchronous reset without the need of a tri-state nand gate.

    [​IMG]

    If the input is '1' and the CLR_H is true then the '0' from the GND is stronger and the input to the inverter is '0' instead of '1' and if the CLR_L is true then the '1' from vdd is stronger and the input to the second inverter is '1'. Is this correct?
    (sorry about the bad figure)
     
  4. WBahn

    Moderator

    Mar 31, 2012
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    I don't see how this is a FF at all. How is a value held in this circuit?
     
  5. limbonic

    Thread Starter New Member

    Jul 4, 2011
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    My mistake, it is more like a delay, a non-transparent dynamic dff. i dont need to store data, just delay it. but i need to add an asynchronous reset and i dont know if my thought is correct.
     
  6. tshuck

    Well-Known Member

    Oct 18, 2012
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    Your delay will only be the transmission delay times of each portion of the circuit, not much help there...
     
  7. limbonic

    Thread Starter New Member

    Jul 4, 2011
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    yes, but is this an equivalent to a delay with an asynchronous reset?
     
  8. tshuck

    Well-Known Member

    Oct 18, 2012
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    sure, but you can get the same effect with an AND gate without the risk of burning your transistors...
     
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