Hi,

So i am having some issues understanding how to solve this problem.

What is the Function realized at Y in the CMOS circuit shown in figure P.7.18 (Figure attached as a Jpeg file)

I looked at a previous example in the book ExampleP. that had a somewhat similar circuit and tried to understand how they came up with that specific function....
(Figure attached for the example problem)

From the example problem i concluded that when you have Nmos's and Pmos's in parallel you add them? and when they are in series you multiply them? and does this always work?

In General how can i figure out what the Function in the output is suppose to be?

 

First of all in CMOS the N and the P are supposed to be logically equivalent so only look at one of them.
With the PMOS your expression goes straight through but all your inputs are inverted (that is, low signals turn them on which raises the output) while with NMOS your inputs are straight through but the entire expression is inverted (high signal turns it on, but that drops the output).

Which you go with is up to you.

In general yes, the parallel transistors are added (OR) and series is multipled (AND) because think about - in parallel either of the two can be on, while in series both must be on for something to happen.

That example is a bit strange because of those transistors with Theta on the gate.
Anyway, let's just look at the NMOS.

You have 3 possible current paths.
Through A and B, through A and C, or through D and E.
Notice already you get a logic function:

AB + AC + DE
A(B + C) + DE

That's the logic to pull down the node N1. However, your output Y is N1 inverted by M6 and M7, so you get the same expression:
Y = A(B + C) + DE

I guess this is assuming the NMOS are pulling down harder than MP is pulling up, not really sure what it's doing there.

With your question, it works the same way.
3 current paths through NMOS - CB, D, or A
2 through PMOS - BAD or CAD