See figure attached for problem statement.

I tried to draw a timing diagram for this, but I wasn't sure what was going to happen at the first positive edge of the clock.

Inputs of both flip flops are dependent on the outputs of the other flip flop.

So how do I decide the first outcome after one positive edge of the clock? There must be some assumptions I'm allowed to make that I'm missing.

I think if I got the first pulse down I could manage with the rest.

Any ideas?

 

So how do I decide the first outcome after one positive edge of the clock? There must be some assumptions I'm allowed to make that I'm missing.

First use clear input to reset the circuit and the "apply" the clock.
So after the reset Q1 = 0 and Q0 = 0
So J of a first FF0 is in 1 state
And my answer is this

 

First use clear input to reset the circuit and the "apply" the clock.
So after the reset Q1 = 0 and Q0 = 0
So J of a first FF0 is in 1 state
And my answer is this

So how would we "describe" the functional behaviour of this circuit?

Is it enough to just give a timing diagram?

 

So how would we "describe" the functional behaviour of this circuit?

Is it enough to just give a timing diagram?

No, time diagram is not enough.
This circuit is frequency divider
Fout= Fclk/3

 

No, time diagram is not enough.
This circuit is frequency divider
Fout= Fclk/3

So for every 3 pulses of the clock we get one pulse at the output?

 

So for every 3 pulses of the clock we get one pulse at the output?

yes, you right