Designing an up counter?

Discussion in 'Homework Help' started by serg_zone, Dec 2, 2006.

  1. serg_zone

    Thread Starter New Member

    Dec 2, 2006
    4
    0
    I have the following question which is confusing me a bit.
    Design a counter that counts in the sequence 0,1,3,6,10,15, using four D flip-flops as memory elements and natural binary encoding.
    I am familiar with designing an up and down counter, but this i'm not sure about. I suppose the counts doesn't get reset to 0 it's just going to stop at 15.
    The first thing i did is i created a state table for present and next states. which looks like this (Note, each bit in present and next states is represented as Qn)
    0000 -> 0001
    0001 -> 0011
    0011 -> 0110
    0110 -> 1010
    1010 -> 1111

    Then i came up with the folling 4 equations for the circuit.
    D3 = Q1Q0'(Q2 XOR Q2)
    D2 = Q3'Q2Q1Q0 + Q3Q2'Q1Q0'
    D1 = Q1Q0'(Q3 XOR Q2) + Q3'Q2'Q0
    D0 = Q3'Q2'Q1' + Q3Q2'Q1Q0'

    The circuit is very complex lol. I'm not sure if what i'm doing is actually any good. Any pointers would surely help. Thanks in advance.
     
  2. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
    282
    Hi,

    Being a technician, I would draw the logic elements and see if the right D came up high following the previous state of the flip-flops. I use a lot of paper when I do logic designs.
     
  3. serg_zone

    Thread Starter New Member

    Dec 2, 2006
    4
    0
    Well, i am able to come up with the correct next states using the equations i have provided in the first post. I'm just confused what the counter should do once it hits 15. Do i reset it back to 0 or does it just stop there?
     
  4. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
    282
    Hi,

    That's not explicit in your original statement. I guess you could generate a carry and go back to 0000 as extra credit.
     
  5. ayaznaqshband

    New Member

    Jan 8, 2008
    3
    0
    Do not hijack multiple threads. If you have a question start your own thread.
     
  6. scubasteve_911

    Senior Member

    Dec 27, 2007
    1,202
    1
    Hello,

    I believe that this circuit should repeat back to its initial state. I don't really know what natural binary encoding means, so can someone clarify? What you have written is not gray-coding, which was what I thought it might have been.

    I would have encoded the input as 0000, 0001, 0010, 0011, 0100, 1000. The simplicity of this will help out with your logic complexity. If you had less states, you could have used one-hot encoding to make things extra easy.

    Then, you draw the Karnaugh map for each next state variable in the row, using unused states as "Don't Care" states to help minimize logic. You then need to write the output in terms of the present state, which is a Moore-type FSM. Then, just add the four D-FFs, surround with logic! Remember to use the Q and Qnot outputs of the FF, since it can save an inverter.

    Steve
     
  7. scubasteve_911

    Senior Member

    Dec 27, 2007
    1,202
    1
    Just for clarity... The table should look like this

    CURRENT STATE | NEXT STATE | OUTPUT
    y3 y2 y1 y0 | Y3 Y2 Y1 Y0 | D3 D2 D1 D0

    Where Y is your FF input, y FF output, D output.

    structure should be: Combinational logic --> FFs --> Combinational logic --> Output

    K-Maps needed for Y, D.

    Steve
     
  8. techroomt

    Senior Member

    May 19, 2004
    198
    1
    if you are familiar with up/down counters with stop features, additional gates that "watch" for a particular bit pattern, then maybe you could incoporate some gate logic to watch for a bit pattern (your first one would be a 0010) to provide an asynchronous "set" condition on the flip flops to a 0011. next valid clock would increment to a 0100, which gate logic would "watch" for then force a "set" of a 0110, etc.
     
  9. scubasteve_911

    Senior Member

    Dec 27, 2007
    1,202
    1
    Yes, this is true, but you need a systematic method to do FSMs like this one. I have done some very complex ones on exams and in assignments that I would have never guessed in a million years :) My professor liked it when you have to do 37 gates and 3 FFs for a FSM, and even better when you were to draw it in complex-CMOS :p

    Steve
     
Loading...