Designing a JFET amplifier

Discussion in 'Homework Help' started by Sharpiedeluxe, May 3, 2010.

  1. Sharpiedeluxe

    Thread Starter New Member

    Apr 1, 2010
    I'm working on designing a JFET amplifier for a project for my class. I have a schematic, and some guidelines, but I'm not too sure that the schematic and my results make sense. I posted an image of what it should look like, except replace the transistor with a N-channel JFET (2n3819). Should be common source. My first question is: can I have an upper and lower resistor for the source transistors with only one being bypassed? I've seen most CS configurations with just one source resistor in parallel with a capacitor, but my professor gave us this design :confused:

    Right now, I have an Idss of 10mA, Id of 1mA, Vp of |-4|, Vgs = -2.735, so my gm = 1.581.
    I want to get a gain of -3, in using an ac analysis. For an ac equivalent circuit, I think u = gm*rd, where u is the amplification factor, rd is the output resistance. For some reason, during calculation I find that u and rd become negative quantities, does this seem incorrect? I can provide all circuit component values if needed, and I will try to draw the equivalent small signal circuit so I can post it here.

    Thanks for the help, please let me know if I should clarify anything.

    Last edited: May 3, 2010
  2. PRS

    Well-Known Member

    Aug 24, 2008
    In a practicle implematation you need a bias circuit at the gate unless you're allowed to use the dc offset of your signal generator. A FET is capable of self bias which just means you put a resistor between the gate and ground. Then you couple the signal to the gate through a gate capacitor.

    If you have calculated actual values for your resistors by all means post them so that we can work with the actual circuit. If you need to draw it on a piece of paper, scan it, make a file and post that. Or use paint.
  3. rudi

    New Member

    May 3, 2010

    I think that the transfer function should return a negative value, as the FET inverts the signal from input to the output.
    I see nothing wrong with the biasing, however, rd should be positive and also the gain's expression more complex as the lower resistances will interfere in the transfer function at the denominator...