Designing a digital system

Discussion in 'Homework Help' started by EngIntoHW, Sep 1, 2010.

  1. EngIntoHW

    Thread Starter Member

    Apr 24, 2010
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    I'm trying to design the following digital system:

    8 inputs (in each clock rise, 8 bits are received).
    8 outputs

    CLK: input -----> Output
    1:::: 00101010 -> 00100000 (index 3 = 1)
    2:::: 01001001 -> 00001000 (index 5 = 1)
    3:::: 01010101 -> 00000100 (index 6 = 1)
    4:::: 01001000 -> 01000000 (there is no '1' at indexes 7,8 of input, so we start from the beginning, and therefore index '2' = 1).

    How would you design such system using digital logic? (FFs, logic gates, counters, etc).

    Thank you.
     
    Last edited: Sep 1, 2010
  2. Flow

    Member

    May 30, 2010
    37
    1
    It's a simple state machine, look em up on the net and get the equations via state tables and karnaugh maps. With the equations you can draw the circuit diagram right away.
     
  3. EngIntoHW

    Thread Starter Member

    Apr 24, 2010
    128
    0
    Hey,

    How can you do it with a state machine?
    wouldn't you end up with lots of states?
     
  4. Flow

    Member

    May 30, 2010
    37
    1
    I can see 4 states, though I find that systems description kind of confusing.

    What's the relation of the inputs and the clock? Are these states in a strict sequence?
     
  5. EngIntoHW

    Thread Starter Member

    Apr 24, 2010
    128
    0
    Hi again,
    Thanks for your help.

    In every clock, 8 bits are received as inputs (they are received in parallel, meaning the machine has 8 inputs, not 1).

    What are the 4 states you thought of?
     
  6. EngIntoHW

    Thread Starter Member

    Apr 24, 2010
    128
    0
    Also,
    Here is what I thought of:

    [​IMG]

    What is your opinion please?
     
  7. Flow

    Member

    May 30, 2010
    37
    1
    How many input / output combinations do you have? Are there just these four? If that's it -> easy. If there are more, I don't get your description of what the system is supposed to do, sorry.
     
  8. EngIntoHW

    Thread Starter Member

    Apr 24, 2010
    128
    0
    Hey,
    No, there're not just these four sequences.

    This's what the system is supposed to do:
    8 bits are received in clock #1:
    say: 0110-1010
    '1' appears for the first time in index #2, so the system outputs: 0100-0000

    8 bits are recieved in clock #2:
    Say: 11101101
    '1' appears for the first time in index #1, but now we treat only indexes above index #2, so the system "sees" '1' in index #3 for the first time, and therefore outputs: 0010-0000.

    8 bits are recieved in clock #2:
    Say: 1100-0000
    now, no '1's appear in indexes above index #3, so we start from the begninnig - and see that the first '1' appear in index #1, so the system outputs: 1000-0000

    Got it?
     
  9. Georacer

    Moderator

    Nov 25, 2009
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    This seems quite complex to do with logic circuits. It can be done of course, but it's gonna be big, except someone has a genius idea.

    Have you thought of using a microprocessor?
     
  10. EngIntoHW

    Thread Starter Member

    Apr 24, 2010
    128
    0
    Hey Georacer,

    What do you think of my solution? (Post #6).

    It isn't that complex a solution.
     
  11. Georacer

    Moderator

    Nov 25, 2009
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    1,266
    The idea is simple, I won't argue with that. But the implementation and orchestration of the ideas is the one that troubles me.

    The only way I can think to construct that "machine" in the middle is to build the 8 outputs and set each one to compare its bit with all the previous outputs. The first output will be 1 if the input is 1. The next will look at the previous output and if it is 1 it will ignore the input. The third output will need to look at both previous outputs, and so on. That gives us a lot of gates. If only someone had a cleverer idea...

    You also need a way to find and store the number of shifts. This would be easy with a 8-to-3 encoder. Are you allowed to use one of these? If it has an enable input you won't need to use a Flip Flop to store the number of shifts.

    The synchronization of these elements is also a task to consider.

    If you are familiar with this scale of build, sure go ahead and try it. But if you have an available simulation software use it before breadboarding. It can save you a lot of time of wiring and rewiring.
     
  12. EngIntoHW

    Thread Starter Member

    Apr 24, 2010
    128
    0
    Hey,

    Thanks for your great comments.

    This "macnine" in the middle is very simple to build.
    A 8-to-3 priority encoder receives the 8-bit input, and its output connects to a 3-to-8 decoder, and the latter's output goes to the machine's output.

    As for synchronization, you're right, I'll need to connect a 3-bit DFF following the Encoder.
     
  13. Georacer

    Moderator

    Nov 25, 2009
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    A priority encoder, right? I' ve never used one, that's why I didn't think of it. I' ve read about it though in my microcomputers class. Good choice, that should untie your hands.

    In order to store the 3-bit result, use a 4-bit register. This way you can control its "write" function.

    Will you use a manual clock for the system?

    If you come up with a schematic, post it and I 'll try to simulate it.
     
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