Hi,

I'm required to design a 3 stage multistage BJT amplifier with the following requirements.

stage 1: bjt differential pair with current mirror load and tail current
stage 2: bjt gain stage with an active load and current mirror bias
stage 3: bjt low output impedance stage

The amplifier can contain: frequency compensation capacitor, resistor for setting the bias reference current, potentiometer for offset voltage control. The amplifier is to be supplied by two DC supply voltages: VCC =+10V and VEE=-10 V.
The amplifier should have a minimum voltage gain of 2000 and an output resistance less than 100 ohms.


I've read on multistage amplifiers all day today and hasn't got a clue on how to approach this problem.

ANY kind of help or pointers or hints will be very much appreciated. Thank you!!

 

Start by drawing the parts you do understand, like a differential pair with a potentiometer in the emitter circuit to balance the input offset. Then draw a constant current circuit, knowing that it is going to be used to drive more than one mirror. Figure out that the gain will have to be accomplished in 2 stages and the square root of 2000 is about 45. Look up the schematics of the insides of op-amps in the National Semiconductor website. Op-amps use the building blocks you have to work with. You can see how those building blocks are configured and mated to each other in op-amps. Keep in mind that monolythic chips use tricks that you can't use with discreet components, like matched gain transistors and temperature tracking.

Good luck. You have some work ahead of you.

 

Hmm so I should have a gain for about 45 for stage 1 and stage 2? Would it also work if I have say 20 and 100?
And what kind of design should I do to make it have a low output impedance?

Thanks for your help!

 

Hi,

I'm required to design a 3 stage multistage BJT amplifier with the following requirements.

stage 1: bjt differential pair with current mirror load and tail current
stage 2: bjt gain stage with an active load and current mirror bias
stage 3: bjt low output impedance stage

The amplifier can contain: frequency compensation capacitor, resistor for setting the bias reference current, potentiometer for offset voltage control. The amplifier is to be supplied by two DC supply voltages: VCC =+10V and VEE=-10 V.
The amplifier should have a minimum voltage gain of 2000 and an output resistance less than 100 ohms.


I've read on multistage amplifiers all day today and hasn't got a clue on how to approach this problem.

ANY kind of help or pointers or hints will be very much appreciated. Thank you!!

Have you given us all the parameters? Is there a load resistor specified? Is there minimum peak to peak voltage swing? How about a minimum input resistance? And is there a specified bandwidth? These are important items to know before getting started.

 

Have you given us all the parameters? Is there a load resistor specified? Is there minimum peak to peak voltage swing? How about a minimum input resistance? And is there a specified bandwidth? These are important items to know before getting started.

Hmmm no none of that are specified in the question, I'm supposed to just design this amplifier and measure it's performance and characteristics.

 

Hmmm no none of that are specified in the question, I'm supposed to just design this amplifier and measure it's performance and characteristics.

Okay, so be it. That just gives us a little more freedom. As Bychon said, start by laying out a possible overall amplifier. You can draw it with PAINT if you don't have a spice program. If you can't do this, I'll set one forth for you and everyone else to criticize. Gotta go to work right now.

 

45 times 45 is 2025. 10 times 200 is 2000. 133 times 15 is 1995. Got it now? Any two gains that multiply up to 2000 will work. As for "low impedance outputs...they are usually accomplished with a emitter follower configuration. Emitter followers don't have voltage gain. That's why you need to get the gain done in the first 2 stages.

 

My take on the problem is blocked out in the attachment. Notice I anticipate a complimentary pair output to ensure Rout<100ohms. These tend to have an attenuation factor between .8 and .9, so I assumed the worst case and gave the voltage gain stages (1 and 2) 50V/V each for a gain of 2500, which, when multiplied by .8 is 2000 V/V. Any thoughts on this? I think it is just as easy to design for 2500 as it is 2000 and the complimentary pair ensures success with regard to Rout.

And perhaps the 2nd stage should be another diff. pair with active load? Probably. As someone said above, you are being asked to build a simple op amp. The 2nd stage should probably be a diff pair with double ended inputs so as to maximize the gain from stage 1.

And, as someone above mentioned, the current mirror could serve both stages 1 and 2. So ignore the simple CE stage 2 in my attachment. Stage 2 is, indeed, a differential amp with active load and current mirror.

And the requirement of an active load complicates things such that, yes, you are being asked to build a discreet transistor version of a commercial IC op amp.

 

By the way, is there a design parameter such that the output voltage must have a zero dc component? If not, why the pot?

 

Thanks so much guys, with your help and more reading, I think I'm good with this problem.

Following Paul's ideas, I'm going to make the first and second stage to have gain of 50 each, and an emitter follower in the last stage.

Just gotta simulate it in pspice later today.

thanks again for the help

 

Cool, mattc2, I hope for your success! If you have any more questions, feel free to ask. I'm not an electronics guru, but I can help you reason stuff out and there are a lot of people posting here who know more than me. Good luck!