Hello all!

I've been set an assignment recently to build a working 8088 system. Now I've spent a few hours reading up on the subject and I think I have most of it down.

I'm having a few problems with the 16-key keyboard/display interface unit and the programmable I/O interface.
For the keyboard I'm using a 4x4 key matrix, the output of which is connected to a 8279. The SL pins of this are connected to 2 3-8 decoders ( one of which is fed into the matrix ( pins 0 - 3 ), the other being fed into the LED digit display )

The interface I'm using is the 8255, I've configured this to be :

PA - Input
PB - Output
PC - Output

We've been asked for a 8/in 16/out interface in the brief

My question is to connect these two devices together, am I right in thinking that I will use the output of the 8279 ( PINS OUTB0-3 and OUTA0-3 ) to be the input of the 8255 ( Pins PA0-7 )??

Also, do the outputs of PB and PC then make their way onto to the CPU's address buffer?

I've included a diagram of the 8255 that I'm working from. As you can see it has address pins connected to it. I'm still scratching my head try to think of what they do, I've looked at notes but they seem to skip over the A0 - A7. Any help on where to connect them would be much appreciated.


Thank for now, although I don't think it's going to be the last question I have :L

 

Google can be very helpful when working with very old critters like the 8088. There are 7,920,000 hits on "8279" alone. This one might be useful - http://www.csee.umbc.edu/~plusquel/310/slides/8086_IO3.html.

You have the right idea for the address selection for the 8255. The net effect is that multiple input NAND gate. What you need to devise is a mixture of gates whose combined output is the equivalent of the pictured NAND.

 

Thanks for the reply. I'm still confused as to what actually connects up to each other.

Am I right in thinking that PB and PC ( outputs ) are both connected to the address bus of the CPU.

Also, are the A0 - A7 data pins of the 8255 connected to the input of PA0-7?

The NAND gate bit still confuses me though...

 

ve made a little picture to try and detail what I want to do. I've left out the 74318 connections for the control lines of the Ram and EPROM, and the memory itself for simplification. I know it's a rough diagram but I hope it's okay.

The brief for the assignment was:

48K Bytes of EPROM for programme memory (choose the components that will give you the exact size of memory).

12K Bytes of RAM for Data memory (choose the components that will give you the exact size of memory).

A Keyboard/Display Interface unit (should support an 8-digit LED display and a keyboard of 16 key switches).

A programmable I/O Port (8 I/P lines and 16 O/P lines, mode 0), Give the right code that will initialise the chip to the required mode.

As you can see I'm still stumped as to the A0 and A1
For the EPROM and RAM I plan to use combinations of 16k, 8k and 4k.as said he wants exact values

 

The 8088 data bus will have to connect to memory and the interface chips through a buffer. Probably a 74LS245 would do. The direction pin will be under the control of the Read/write signal from the 8088.

Your total memory is 60K, leaving 4K of space for I/O. 8088's may require the lowest and/or highest addresses available for proper operation, so check the data sheet for the I/O space addresses.

I'd get the data sheets for all the chips and see what the connection and addressing requirements are. All these chips are very old so there a zillions of examples on the web. You'll be having fun decoding lots of chip select signals.

 

I shouldn't for the double post but this is all over the web.
http://www.cs.binghamto.edu/~reckert/sbc.htm

 

Doesn't leave much to the imagination, does it?