design of a digital lock

Discussion in 'The Projects Forum' started by rakeshk_87, Dec 7, 2008.

  1. rakeshk_87

    Thread Starter New Member

    Mar 16, 2008
    2
    0
    hi
    i need to design a digital lock using pulse mode sequential circuits.the lock is controlled by 5 pulses. <x1>,<x2>,<x3>,<INIT>,<RESET> the lock is opened when a sequence of six pulses are applied. i used the sequence <x1>,<x2>,<x2>,<x1>,<x1>,<x3>. I used the following states to design the FSM S0,S1,S2,S3,S4,S5,OP,AL. Once the correct sequence of lock is applied,it will be opened by a level output signal Z1=1. when an incorrect input pulse is entered ,the lock will advance to an ALARM state(AL) where Z2=1,The lock will remain in the ALARM state indefinitely until it is RESET by an authorized personnel who has access to the input <RESET>.When a pulse is applied to the RESET input,the lock will return to the initial state in which both Z1 and Z2 are 0. the <INIT> is used to initialise the lock only after installation and maintainance. no user has access to this input.
    I designed the circuit using T flip flops but i am having trouble designing the <INIT> and <RESET>. I am designing it using LOGIC WORKS .I cant figure out how i can make it not accessible to the user. Can someone help me?
    THANKS
     
    Last edited: Dec 8, 2008
  2. Wendy

    Moderator

    Mar 24, 2008
    20,764
    2,534
    As always, when asking for help with a circuit, schematics are a must.
     
  3. rakeshk_87

    Thread Starter New Member

    Mar 16, 2008
    2
    0
    Hi i am sorry i did not attach the schematic.I have attached it now.
    Thank you
     
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