hello there
i has an assignment due to 1 week later, but until now seems i can't understand the meaning of the problem given by my teacher
the problem is:
design a vhdl code for 2 -ways associative cache
* 16 bit adress
* 8 set
* 8 byte block
* random replacement
* output hit/miss
please someone share some references that i can learn , or vhdl code so i can understand.
thanks
best regards
i has an assignment due to 1 week later, but until now seems i can't understand the meaning of the problem given by my teacher
the problem is:
design a vhdl code for 2 -ways associative cache
* 16 bit adress
* 8 set
* 8 byte block
* random replacement
* output hit/miss
please someone share some references that i can learn , or vhdl code so i can understand.
thanks
best regards