design 3 stage op amp

Discussion in 'Homework Help' started by ZMAN Z28, Oct 26, 2005.

  1. ZMAN Z28

    Thread Starter New Member

    Oct 26, 2005
    3
    0
    Hello:

    I hope you guys can help me design a 3 stage op amp? Here are the specs:

    Class A amp
    Cap coupled
    Overall gain of 100
    use 3 3904 or 4401 transistors
    20 volt power supply
    load will vary from 1k Ω to 10 k Ω
    The first 2 stages have to be CE, and the final stage is CC

    Thanks:

    ZMAN
     
  2. mozikluv

    AAC Fanatic!

    Jan 22, 2004
    1,437
    1
    hi zman,

    is that a 20v single rail or a +/-10v dual rail supply or +/-20v dual rail

    moz
     
  3. n9352527

    AAC Fanatic!

    Oct 14, 2005
    1,198
    4
    This is a classic assignment for analogue design course in university.

    The way to design it is to work from back to front.

    1. Start from the output and work out the maximum and minimum output current that is required.
    2. Calculate the emitter current so that the variation of the output load doesn't affect the biasing point that much (stay around 0.5Vcc).
    3. The output voltage has to be a half of the supply voltage for maximum swing.
    4. Calculate the Re.
    5. Calculate the Vb.
    6. Calculate the base current required from the hfe of the output transistor (add some margin).
    7. Calculate the biasing resistors network so that the base current doesn't affect the current through the biasing potential divider (stay on the required Vb for Vo=0.5*Vcc).
    8. Calculate the values for the upper and lower resistors legs so that Vb is right.

    You have to decide how much gain to assign for the middle transistor and the input transistor. Any gains that multiply to 100 are acceptable, e.g. 10 and 10. I would go for lower noise gain on the input stage for improved noise performance.

    The middle and input stages calculation are similar, except that now you have to calculate the gain from the Rc and Re and Ic is calculated with Rc and Re.

    The fun part is when there stages are dc coupled (no coupling caps). Then you have to match the dc level of the adjacent stages as well.

    Have a look at the tutorials on this site for references.
     
  4. n9352527

    AAC Fanatic!

    Oct 14, 2005
    1,198
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    Forgot to mention that the RoT is that to minimise the loading on the base bias potential divider from the base current, the current through the potential divider is approx. 10 times the base current.

    This is valid for most circuits where one leg of potential divider, or such circuits, is not constantly loaded.
     
  5. ZMAN Z28

    Thread Starter New Member

    Oct 26, 2005
    3
    0
    Thanks:

    I'll post the circuit after I get it complete.

    Z
     
  6. mozikluv

    AAC Fanatic!

    Jan 22, 2004
    1,437
    1
    hi zman,

    here's a circuit that might help you out in your design. you will notice that stage 1 & 2 is cap coupled while stage 2 & 3 is direct coupling. likewise stage 1 & 2 has an emitter bypass caps.

    you must also bear in mind that any signal source contains an internal resistance w/c we must take into maccount when we compute for the overall system gain.

    likewise, with the use of by-pass caps the input resistance is also affected.

    moz
     
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