# Deriving logic expression from CMOS circuitry

Discussion in 'Homework Help' started by jegues, Sep 30, 2010.

1. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
735
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See figure for problem statement.

I'm curious as to the procedure for solving a question like the following.

What do you look for?

Our professor hasn't explained how to solve these types of questions so I don't really know where to start.

Thanks again!

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Last edited: Sep 30, 2010
2. ### Ghar Active Member

Mar 8, 2010
655
72
Making a truth table is the best way to first understand it I think.

After that you can just look at this and write it down...

With CMOS you only need to look at either the NMOS or the PMOS since they are complementary. If they aren't complementary there is something wrong.

Just keep in mind that a high input to an NMOS lowers the output while PMOS is the opposite.

3. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
735
43
So in other words, I can simply focus on the PMOS and write a truth table?

Isn't a 5 variable function going to give me a pretty huge truth table?

There has to be a simplier way!

Last edited: Sep 30, 2010
4. ### Ghar Active Member

Mar 8, 2010
655
72
Yes it will, you will have 32 rows.

This why you generally start learning with simpler circuits... in your other thread you were asking about NAND and OR gates and such... try drawing those and figure out what the transistors are doing.

5. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
735
43
If I'm focusing on the the NMOS portion of the circuit, it looks like we have two NAND's in parallel.

These two NAND's are also in parallel with a NOT.

Is this correct?

EDIT:

After looking at it again... Is it something like the following:

(NAND)NOR(NAND)NOR(NOT)

Last edited: Sep 30, 2010
6. ### Ghar Active Member

Mar 8, 2010
655
72
Yep, that's right.

Being in parallel means what for a logic function?

7. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
735
43
It would be like an NOR, correct?

8. ### Ghar Active Member

Mar 8, 2010
655
72
You're on the right track but you need to be careful. I don't remember all the distributive properties of logic so maybe it's still the same but really, what you're doing is this:

Logic function = NOT (pulldown network)

The pulldown is x5 + x4x3 + x1x2, so the complete function is NOT(x5 + x1x2 + x3x4)

Alternatively for the PMOS the logic function is equal to the pullup network but each input is individually inverted because PMOS turns on for a low input.

9. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
735
43
If I can consistently draw conclusions like the following,

then the rest of the work is easy! But when you say the pulldown network I think of the two NAND's in a NOR

Now how would I NOT two NANDS in a NOR? This is where I get confused. I'm curious to know how you figured out the pulldown was x5 + x4x3 + x1x2. Can you explain?

It's just drawing those conclusions that is the difficult part.

So the function would be,

$\bar{x_{5}}(\bar{x_{4}} + \bar{x_{3}})(\bar{x_{1}} + \bar{x_{2}})$

10. ### Ghar Active Member

Mar 8, 2010
655
72
Yep that's right.
You should always test your conclusions. It's a part of learning... try whatever comes to your mind then figure out whether it works and especially why it works or not.

A truth table is a pretty reliable way to test these things because it's so brute force. There's essentially no thinking to mess you up.

11. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
735
43
How did you come to the conclusion for what the pull-down network was?

12. ### Ghar Active Member

Mar 8, 2010
655
72
NMOS is straightforward because a high input turns on the transistor.

There are 3 branches which can pull down your output.
The first is just one transistor, controlled by x5
The second is two transistors, both must be on, controlled by x3 and x4.
The third is again two transistors, this time controlled by x1 and x2.

If any or all of those 3 branches is conducting your output will be low.
That means the 3 branches are OR'ed together.

Clearly the two transistors in series are an AND operation.
So you get that the output will be pulled down when:

x5 + x1x2 + x3x4

Since the logic function is defined as what makes it high you need to invert that:
NOT(x5 + x1x2 + x3x4)

I don't like working with NAND and NOR because they're too complicated to think about.

13. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
735
43
Thank you for explaining, this post gives alot of insight!

14. ### Georacer Moderator

Nov 25, 2009
5,142
1,266
We did all the above thinking by taking as a given that the circuit is correctly designed as a logic function and will always connect the output with either the Low or the High voltage, not both at once, but always with one of them.

If there wasn't that certainty, shouldn't we explore the upper part of the circuit too?

15. ### Ghar Active Member

Mar 8, 2010
655
72
You can definitely check out both pull up and pull down networks if you're feeling paranoid.

Normally you can see the symmetry.
PMOS vs NMOS you simply replace series with parallel.

In this NMOS you have:
x5 + x3x4 + x1x2
In PMOS (ignoring the inversions) you therefore have:
x5(x3 + x4)(x1 + x2)

16. ### Georacer Moderator

Nov 25, 2009
5,142
1,266
Yeah, I see what you mean about the complementary design. It can be verified with a quick glance on the upper circuit. I don't know, I 've been brainwashed with trap-questions all those years at uni that I look behind my back even when I 'm going to bed.

17. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
735
43
Sorry to ressurect this thread again but I still have some concerns about what procedures to follow.

Concern #1: Drawing the CMOS circuit from a given function.

Example: F = x + y,

Okay, I want to draw the NMOS network first since it is easier to understand.

Values that satisfy x + y will give me a 1 at the output, but if I want to draw NMOS first I want to look at values that give me a zero at the output.

So I NOT(x+y), giving me NOT(x) AND NOT(y).

So for the NMOS network I'm going to draw x and y in series and then have one final inverter before the output. For PMOS I'll simply draw the complement of the NMOS network.

Is this the correct "procedure" I should be following?

Concern #2: Deriving a function from a CMOS schematic.

I'm going to first derive a function from the NMOS network and then NOT that function to get the desired function.

In NMOS, if the transistors are in series then they are being NAND'd and if they are in parallel they are being NOR'd.

So from NMOS let's say I come up with a function like xy + z.

Then the ACTUAL function will be (NOT(x) + NOT(y)) AND NOT(z)

How does all this sound?

Do I have my head on straight!?

What if the function given was, F = NOT(x) + y?

NOT(F) = x AND NOT(y)

I don't know how to draw this because I only want the y input to be complemented, not everything. How do I manage?