delay locked loop

Discussion in 'The Projects Forum' started by suzuki, Aug 24, 2011.

  1. suzuki

    Thread Starter Member

    Aug 10, 2011
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    0
    Hi all,

    does anyone have a description of a DLL in layman's terms? I understand that it is similar to a PLL, which locks the frequency and phase of the VCO to the reference signal by comparing the freq/phase of the VCO with the freq/phase of the reference signal.

    From what i have understood, the DLL compares the input reference signal with the delayed version of the input reference signal. Is this delay controlled by the (voltage) output of the phase detector?

    I guess this is where i become sort of confused. if the loop is not locked until the error is zero (or constant), when we lock, wouldnt the reference signal and the output signal be the same? what's the point of doing that? I suppose in the PLL, you can add a multiplier/divider in the feedback to synthesize other frequencies, but i can't quite wrap my head around the DLL functionality.

    i guess that brings me to the final question, can we use the DLL to get rid of a phase difference between two signals? i.e. if i had a ac signal pass through an inductor, could i delay the voltage signal such that the current and voltage are in phase again?

    Thanks in advance. :)
     
  2. Hi-Z

    Member

    Jul 31, 2011
    157
    17
    Yes, the phase detector output is used to control a voltage controlled delay element, via a filter/amplifier. The dynamics of such a loop are much simpler than a PLL, as there is no integrator (represented by a VCO) present, so there is no need for a proportional/integral loop filter, and you end up with a first order (as opposed to the usual second-order) loop.

    You would use it to negate delay in a clock distribution system, in order to be able to align data to the clock. An example would be within an ic, where clock tree delay would otherwise present severe problems. There are other applications too.
     
  3. Hi-Z

    Member

    Jul 31, 2011
    157
    17
    I haven't been very explicit in my explanation regarding getting rid of delay in a clock path. Basically, what you're doing is adding sufficient clock delay, such that the total clock path delay becomes equal to exactly one clock cycle (or perhaps several cycles).
     
  4. suzuki

    Thread Starter Member

    Aug 10, 2011
    119
    0
    Hi,
    thanks for your reply. i sort of see what you are getting at. Is it correct to say that you are delaying a signal until it aligns with the clock signal?

    I suppose what has me really confused is how is the clock signal and the input signal compared? According to this diagram http://upload.wikimedia.org/wikipedia/commons/f/f5/Delay_locked_loop.png (and some others i have seen), there is one input signal and it is compared with the delayed version of ITSELF. i can't say i really see the value in doing that, since you would have to explicitly known when the clock is changing to align your signal with the clock signal.
     
  5. Hi-Z

    Member

    Jul 31, 2011
    157
    17
    The application I have in mind is where you have a clock path with undesirable (and undefined) delay. You add extra controllable delay in the clock path and use the phase comparator to adjust this delay so that the total delay is equal to exactly one clock cycle (it could actually be several clock cycles, but it comes to the same thing).

    Using this, you can remove all apparent delay from the clock path. You could have used a PLL to similar effect, but for this particular application I think the DLL is better and easier to implement (particularly in the context of an ic).

    By the way, it's conceivable that you're talking to the first user of a DLL here: I designed a DLL (except I hadn't heard of such a thing) for a different application in the early '80s, and my boss at the time said "I suppose you'd call it a delay-locked-loop" (maybe the first use of the term??).
     
    suzuki likes this.
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