delay line memories and sram

Discussion in 'Homework Help' started by bhuvanesh, Aug 31, 2014.

  1. bhuvanesh

    Thread Starter Member

    Aug 10, 2013
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    2
    i couldnt differentiate delay line memories and sram.Since both using flipflops.who they are differentiated whats the dis advantage in DL memories.Thank you in advance
     
  2. faley

    Member

    Aug 30, 2014
    94
    13
    Delay lines are sequential- operation similar to shift registers (think LIFO, LILO, FIFO and FILO). Whereas SRAM can be accessed randomly. Given the difference, what do you see as a disadvantage?
     
  3. bhuvanesh

    Thread Starter Member

    Aug 10, 2013
    268
    2
    speed
    delay line require more time ,because it must be in sequence.
    Another question.what makes sram to access data at random unlike delay line memories
     
  4. faley

    Member

    Aug 30, 2014
    94
    13
    By design. The original delay lines were intended to delay, not to provide access to, or allow change of, an individual memory location (bit address) at any given time. As the name implies, the purpose is to "delay" the transmisson of data rather than processing it in real time.
     
  5. bhuvanesh

    Thread Starter Member

    Aug 10, 2013
    268
    2
    why they need delay the transmission?what is the need?
     
  6. faley

    Member

    Aug 30, 2014
    94
    13
    Usually it involves synchronization with another process. Sometimes they're useful in data averaging. There are many reasons.
     
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