Delay line IC - digital

Discussion in 'General Electronics Chat' started by Vindhyachal Takniki, Apr 14, 2015.

  1. Vindhyachal Takniki

    Thread Starter Member

    Nov 3, 2014
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    I am looking for delay line IC for digital signal.
    I have some signal which I want to delay in us range (0-999us) with 1 us increment

    1. I have looked at DS1100-500, that is good but its only for 500ns.
    I can cascade some IC in series to generate delay in us but not for large signal.

    2. For us range I have checked LTC6994-2. It is good IC. Only problem is if I try to delay both edges, the input pulse width can never be less than tDELAY, otherwise no output signal is generated.
    Tdelay is time set for generating delay.
    e.g if set 20us delay, & I send a 1us input pulse, then IC removes it & generate no output instaed of delaying.

    3. On net I have checked many IC all have delay of picosecond or nanosecond.

    4. I want IC to be discrete or programmable by discrete components like LTC6994-2 set delay by selecting resistor value.
     
  2. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    what is the narrowest pulse you want to delay? How exact does the output have to be in relation to the input?
     
  3. Vindhyachal Takniki

    Thread Starter Member

    Nov 3, 2014
    348
    6
    Narrowest pulse is 1us.
    Total delay - 0-999us.
    Increment = 1us

    There will be multiple discrete IC used.AFAIK
     
  4. kubeek

    AAC Fanatic!

    Sep 20, 2005
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    you could use a single FPGA, write a 1000 bit shift register, then clock it at 1Mhz. Or a hole bunch of smaller chips and a lot of glue logic.
     
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  5. Papabravo

    Expert

    Feb 24, 2006
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    What is the purpose of the delay line. The reason I ask is that the technology has been obsolete for a very long time, like maybe 45 years.
     
  6. AnalogKid

    Distinguished Member

    Aug 1, 2013
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    Hold on there, young'un. In 1970, 7400 series TTL was only 4 years old, integrated delay lines were relative new, none were available in surface mount, and silicon delay lines were 15 years in the future. Just sayin. And while you can string together inverters inside a CPLD or FPGA to get short delays, or drive an external RC between pins for medium delays, nothing gets you the stability and repeatability of a tapped LC delay line for single-chip large delays.

    ak
     
  7. AnalogKid

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    A good idea as long as the temporal quantizing error is not a problem at low delay values. If the first shifter output is the 2nd stage so the minimum delay always is at least one full clock period, then at 999 us the timing ambiguity of the output leading edge is approx. -0% / +0.1%. At 1 us delay it is -0% / +100% -ish. That a lot.

    ak
     
  8. MrChips

    Moderator

    Oct 2, 2009
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    Tell us the exact application and we would be in a better position to help.
     
  9. ian field

    Distinguished Member

    Oct 27, 2012
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    Some time back one of the hobby magazines (Possibly EPE) did a delay/echo type of project with one of the popular microcontrollers driving a DRAM.

    That project could probably be adapted fairly easily.
     
  10. MrChips

    Moderator

    Oct 2, 2009
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    This can be done easily with two monostables. But it really depends on the specific application and requirements.
     
  11. AnalogKid

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    Aug 1, 2013
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    We don't need no stinking details...

    Speaking of video system design in the late sixties, broadcast quality video recorders had voltage-variable analog delay lines to correct timebase errors caused by the mechanical nature of the playback system (2" wide magnetic tape). The epitome of the genre was the Ampex AVR-1. It used a voltage-variable analog delay line for the mono signal, switched, binary-weighted fixed analog delay lines for the main chroma corrector, and a switched, tapped delay line for fine tuning down to 10 ns resolution, with unprecedented signal fidelity. Working with another guy, we, uh, borrowed this idea to resurrect an old RCA beast. Wound the inductors by hand, used super-tiny mil surplus variable caps to tune the delays. Diff-gain and diff-phase both below 0.1.

    Following this idea (which is 47 years old), 10 fixed delay lines at 1, 2, 4, 8, 16, 32, 64, 128, 256, and 512 us will span the required range with an almost constant temporal quantizing error. Or, three LTC6994's can be strung together, although thhe selectability is messy.

    ak
     
  12. AnalogKid

    Distinguished Member

    Aug 1, 2013
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    True, but both monostables would have to track and have programmability better than 0.1%? A 10-bit DAC could supply the current, but you'd need super-linear drivers and comparators around the timing caps.

    ak
     
  13. Papabravo

    Expert

    Feb 24, 2006
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    So I remember the programming problems associated with using acoustic delay lines for RW memory. There was no RAM yet.
     
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