Decoupling Networks

Discussion in 'General Electronics Chat' started by Narwash, Jul 13, 2012.

  1. Narwash

    Thread Starter Member

    Jun 27, 2012
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    Hi all!

    I'm designing a basic op-amp circuit and am trying to be really careful with noise. I'm not sure if I went too crazy with decoupling networks though.

    I've attached the circuit diagram I whipped up in LTspice. I haven't calculated any of values yet, but I thought I would post the big picture to see if I'm getting the idea right in terms of decoupling the supply from the circuit, the circuit from the output etc. Hopefully I'm attenuating any parasitic inductance/capacitance in my circuit. Or maybe I mucked something up. That's why I'm posting! :D

    I've also been following this guide on decoupling: http://www.designers-guide.org/Design/bypassing.pdf

    The general specs are as follows:
    It's going to end up being a PCB
    Frequency range: 9 kHz-50 MHz
    Power supply for op-amp: 5V
    Signal to be amplified: approx 70.7uV
    Minimum gain needed: 3.3 or about 5.18 dB

    Not sure if I can get away with a single bypass ceramic cap of .1 uF and have the damping circuit reduce any ringing. Or I could perhaps use a 22 uF electrolytic in parallel with a .1 uF ceramic. Might be interesting to do both and compare.

    Any feedback would be great! Thanks so much! :D
     
  2. Narwash

    Thread Starter Member

    Jun 27, 2012
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    Just an update! Calculated some decoupling/bypass resistors/capacitors/inductors values using the specifications set forth by equations 4 and 5 in the link I posted previously. Also calculated the resistor values for the non-inverting op-amp to produce 30dB gain. I figured I might as well shoot high.

    I also took out two of the inductors as I thought they might just block too much AC. Which is advantageous when decoupling a DC source but not so much from an AC source haha. Definitely didn't think that one through on first post. Rookie mistake! D'oh.

    Anyways, I've attached the updated circuit diagram as well as the Bode plot from LTspice. I'm definitely not getting the bandwidth I want, but I think that's from using a "Universal Opamp" model from LTspice. The Op-Amp I'm going to use when I build the real thing is rated for 50 MHz so unless I screwed up the cap values I should be okay.

    Writing this all out sure helps me get a better grasp of what's going on! :D
     
  3. crutschow

    Expert

    Mar 14, 2008
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    For 30dB gain at 50MHz with one op amp, you would need an amp with a 1.6Ghz gain-bandwidth minimum. Those are difficult to find and difficult to use. For your original gain requirement of 3.3 at 50MHz you need an op amp with at least a 165MHz gain-bandwidth specification.

    The most important thing in decoupling the amp at those frequencies is to use a ground plane with SMD ceramic caps as close to the op amp power pins as possible. For best decoupling run the ground side pad of the SMD cap directly to the ground plane (no vias) and run the power trace directly through the hot side pad of the cap.

    A couple of guides to high speed layout are here and here. You would do well to read them carefully before you layout the circuit.

    You show a single supply op amp. For that you need to bias the input signal at 1/2 the supply voltage (see this). A single supply can not otherwise generate the negative half of the AC signal.

    Why are you decoupling the signal source? Normally you don't filter the source unless it has some noise above the highest frequency of interest that you want to suppress.
     
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  4. Narwash

    Thread Starter Member

    Jun 27, 2012
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    Thanks crutschow! Your feedback is very helpful.

    A couple questions:

    How did you calculate the gain-bandwidth minimum of the op-amp for producing a particular gain at 50 MHz?

    Should I be placing my bypass capacitors right at the op-amp power supply pins, instead of at the output of the op-amp, as mention in the analog devices presentation linked?

    I've made an attempt at biasing the input signal at half the supply voltage using a simple voltage divider, but when I run the simulation in LTspice I get massive attenutation of my output signal (~160 dB). I followed the instructions given by this: http://www.electro-tech-online.com/custompdfs/2008/01/sloa058.pdf and used figure 3, an ac-coupled gain stage, as an example to follow.

    I might have gone a little crazy with the decoupling. I took out the decoupling of the input signal and just put a .1uf cap there. I also reset the resistor values in the non-inverting op-amp to yield a gain of 3.3.

    I've attached the updated circuit. Thanks for all your help! :D
     
  5. crutschow

    Expert

    Mar 14, 2008
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    The gain-bandwidth product is just that. You multiply the desired circuit gain by the desired circuit bandwidth to get the minimum required op amp GBW.

    The decoupling caps should always be as close to the op amp power pins as possible. The output decoupling network you show will kill your signal.

    Oddly, there is a mistake in Figure 3. You always need a DC bias bath for both inputs. Thus you also need to bias the plus input to 1/2 the supply voltage with a 10k ohm or so resistor to the bias voltage. And you probably want to use a larger value resistor for your bias network, say 1k ohm or so. Use a large capacitor at the junction of the two bias resistors to ground to provide an AC ground for that point.
     
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  6. Narwash

    Thread Starter Member

    Jun 27, 2012
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    Neat! Thanks for answering those questions. Weird that's there is an error in figure 3, considering the whole document is on single supply op amp design.

    I've updated my circuit to bias both positive and negative inputs to half the supply voltage as well as re-configuring my output decoupling network. I've just put two caps from the op-amp supply to the negative end of the load, like they do in the analog devices presentation linked previously.

    I'm still getting a ~72 dB attenuation of my output signal when i run the spice simulation, not sure if that's real or just LTspice not modelling my generic op-amp correctly.

    I've posted the updated circuit. Hopefully if it checks out I can then move on to the printed circuit board design. Thanks for all your help! :D
     
  7. Narwash

    Thread Starter Member

    Jun 27, 2012
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    Ooops! I don't think I want an AC ground right next to my AC source. Removed those two caps. Diagram attached.
     
  8. crutschow

    Expert

    Mar 14, 2008
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    You removed the capacitor Cin in series with your Vin source to the plus input (why?), thus the bias circuit is shorted to ground (an AC voltage source has zero DC impedance to ground). You need to add that capacitor back in series with Vin to block the DC bias from Vin.

    Note: You can use the same bias network for both inputs (it's actually better to use just one network because it avoids any offset between the two due to resistor tolerances). You just need one resistor between the plus input and the R3-R4 bias resistors.
     
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  9. Narwash

    Thread Starter Member

    Jun 27, 2012
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    Cool thanks! I'm not sure why I took out Cin. I guess I thought the signal generator would already be cleaning up dc bias internally, but I suppose that's wishful thinking and I should be cleaning up my ac input signal with a cap as a rule.

    Good call on using one bias network. I wasn't sure whether to go with one or two but the difference in resistor values due to tolerances definitely closes the case on that one.

    I've updated the circuit and I think it's good to go. The LTspice simulation is still showing attenuation of about 40 dB but I don't think that's representative of the real, functioning circuit.

    I'm thinking about going for more than one op-amp stage for additional gain. Any advice/tips/common pitfalls for designing a multi-stage op-amp circuit? I'm thinking impedance matching between stages will be the biggest concern.
     
    Last edited: Jul 17, 2012
  10. crutschow

    Expert

    Mar 14, 2008
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    Signal generators, virtual or real, do not "clean up" dc bias. You always need to add a blocking capacitor for that.

    What op amp model are you using? You should see gain, not attenuation.

    R5 should be much larger, otherwise it will shunt the input signal to ground. It should be at least 10k ohm, depending on how low a frequency you want to amplify.

    If you post your .asc file, I can try simulating your circuit.

    Edit: Also, standard op amps will not drive a 50 ohm load. Generally it needs to be 2k ohms or higher.
     
    Last edited: Jul 17, 2012
  11. Narwash

    Thread Starter Member

    Jun 27, 2012
    32
    0
    Cool thanks for the help. I've learned a lot in this whole process.

    I changed the resistor values (the load to 2k and R5 to 10k) and I was able to get a ~9 dB gain all the way to 1 MHz. Thanks! I think the 50 ohm load was screwing everything up. However, I'm a little worried about the phase margin. I get a phase margin of about 105 degrees from measuring the frequency at the 0dB on the gain plot portion of the Bode plot (-70 at ~8.5 MHz). I know that a phase margin of about 60 degrees is desirable to prevent oscillation. Not sure if I've got my understanding of phase margin mixed up. I mean 105 degrees PM sounds stable but not sure if that's real.

    I've attached the .asc file for simulation purposes.

    In addition, for building the actual circuit the two op-amps I was looking at were:

    http://www.analog.com/static/imported-files/data_sheets/AD8651_8652.pdf

    and

    http://www.analog.com/static/imported-files/data_sheets/ADA4895-2.pdf

    The second one has a huge gain bandwidth product and would allow for a gain of 30 at 50 MHz. However, it's in the pre-release stage and I'm not certain I'll be able to get my hands on it.
     
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